From patchwork Wed Jun 8 10:26:44 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Kiszka X-Patchwork-Id: 99402 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id E1D89B6FEE for ; Wed, 8 Jun 2011 20:41:27 +1000 (EST) Received: from localhost ([::1]:57710 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUGCR-0001Fm-J4 for incoming@patchwork.ozlabs.org; Wed, 08 Jun 2011 06:41:23 -0400 Received: from eggs.gnu.org ([140.186.70.92]:53210) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUFyN-0006aO-H7 for qemu-devel@nongnu.org; Wed, 08 Jun 2011 06:26:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QUFyK-0003gv-H3 for qemu-devel@nongnu.org; Wed, 08 Jun 2011 06:26:51 -0400 Received: from thoth.sbs.de ([192.35.17.2]:29016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QUFyK-0003fm-7h for qemu-devel@nongnu.org; Wed, 08 Jun 2011 06:26:48 -0400 Received: from mail1.siemens.de (localhost [127.0.0.1]) by thoth.sbs.de (8.13.6/8.13.6) with ESMTP id p58AQkvH029684; Wed, 8 Jun 2011 12:26:46 +0200 Received: from mchn199C.mchp.siemens.de ([139.25.109.49]) by mail1.siemens.de (8.13.6/8.13.6) with ESMTP id p58AQjw6017096; Wed, 8 Jun 2011 12:26:46 +0200 From: Jan Kiszka To: "Michael S. Tsirkin" Date: Wed, 8 Jun 2011 12:26:44 +0200 Message-Id: <32d12d55df0a3a98b7f05b3be5e896fe148d59f4.1307528800.git.jan.kiszka@siemens.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 192.35.17.2 Cc: qemu-devel Subject: [Qemu-devel] [PATCH 6/7] msix: Align MSI-X constants to libpci definitions and extend them X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add PCI_MSIX_TABLE and PCI_MSIX_PBA, align other MSIX related constant names to libpci style. Will be used for device assignment code in qemu-kvm. Signed-off-by: Jan Kiszka --- hw/msix.c | 24 +++++++++++------------- hw/pci_regs.h | 14 ++++++++------ 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/msix.c b/hw/msix.c index 600f5fb..b20cf7c 100644 --- a/hw/msix.c +++ b/hw/msix.c @@ -16,15 +16,12 @@ #include "pci.h" #include "range.h" -/* MSI-X capability structure */ -#define MSIX_TABLE_OFFSET 4 -#define MSIX_PBA_OFFSET 8 #define MSIX_CAP_LENGTH 12 -/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */ -#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1) -#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8) -#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8) +/* MSI enable bit and maskall bit are in byte 1 in control register */ +#define MSIX_CONTROL_OFFSET (PCI_MSIX_CTRL + 1) +#define MSIX_ENABLE_MASK (PCI_MSIX_ENABLE >> 8) +#define MSIX_MASKALL_MASK (PCI_MSIX_MASK >> 8) /* MSI-X table format */ #define MSIX_MSG_ADDR 0 @@ -58,8 +55,9 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, uint8_t *config; uint32_t new_size; - if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) + if (nentries < 1 || nentries > PCI_MSIX_TABSIZE + 1) { return -EINVAL; + } if (bar_size > 0x80000000) return -ENOSPC; @@ -80,11 +78,11 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries, return config_offset; config = pdev->config + config_offset; - pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1); + pci_set_word(config + PCI_MSIX_CTRL, nentries - 1); /* Table on top of BAR */ - pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr); + pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr); /* Pending bits on top of that */ - pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) | + pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) | bar_nr); pdev->msix_cap = config_offset; /* Make flags bit writable. */ @@ -208,11 +206,11 @@ void msix_mmio_map(PCIDevice *d, int region_num, pcibus_t addr, pcibus_t size, int type) { uint8_t *config = d->config + d->msix_cap; - uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET); + uint32_t table = pci_get_long(config + PCI_MSIX_TABLE); uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1); /* TODO: for assigned devices, we'll want to make it possible to map * pending bits separately in case they are in a separate bar. */ - int table_bir = table & PCI_MSIX_FLAGS_BIRMASK; + int table_bir = table & PCI_MSIX_BIR; if (table_bir != region_num) return; diff --git a/hw/pci_regs.h b/hw/pci_regs.h index 5a5ab89..c17c22f 100644 --- a/hw/pci_regs.h +++ b/hw/pci_regs.h @@ -300,12 +300,14 @@ #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */ #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */ -/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */ -#define PCI_MSIX_FLAGS 2 -#define PCI_MSIX_FLAGS_QSIZE 0x7FF -#define PCI_MSIX_FLAGS_ENABLE (1 << 15) -#define PCI_MSIX_FLAGS_MASKALL (1 << 14) -#define PCI_MSIX_FLAGS_BIRMASK (7 << 0) +/* MSI-X registers */ +#define PCI_MSIX_CTRL 2 /* Message control */ +#define PCI_MSIX_TABSIZE 0x7FF /* Table size - 1 */ +#define PCI_MSIX_MASK 0x4000 /* Mask all vectors */ +#define PCI_MSIX_ENABLE 0x8000 /* Enable MSI-X */ +#define PCI_MSIX_TABLE 4 /* MSI-X table */ +#define PCI_MSIX_PBA 8 /* Pending bit array */ +#define PCI_MSIX_BIR 0x7 /* BAR indication register */ /* CompactPCI Hotswap Register */