drm/nouveau: tegra: Initialize mode configuration

Message ID 20181106162415.3578-1-thierry.reding@gmail.com
State New
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Series
  • drm/nouveau: tegra: Initialize mode configuration
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Commit Message

Thierry Reding Nov. 6, 2018, 4:24 p.m.
From: Thierry Reding <treding@nvidia.com>

Irrespective of whether or not the device has any usable outputs, the
modesetting helpers will try to register all the resources such as CRTCs
and planes. Unfortunately, the helpers rely on drm_mode_config_init() to
properly set up internal data structures. Since the Tegra GPU does not
have a display engine, the Nouveau driver doesn't set this up for Tegra,
which results in the following oops on driver probe:

	[   18.776221] Unable to handle kernel NULL pointer dereference at virtual address 0000006c
	[   18.785401] pgd = 16bb93b7
	[   18.789331] [0000006c] *pgd=ad58c003, *pmd=00000000
	[   18.800757] Internal error: Oops: 206 [#1] PREEMPT SMP ARM
	[   18.806233] Modules linked in: nouveau(+) ttm tegra_drm
	[   18.811457] CPU: 1 PID: 245 Comm: systemd-udevd Not tainted 4.20.0-rc1 #36
	[   18.818324] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
	[   18.824596] PC is at drm_plane_register_all+0x18/0x50
	[   18.824601] LR is at drm_modeset_register_all+0xc/0x70
	[   18.824604] pc : [<c068b938>]    lr : [<c068e45c>]    psr: a0000113
	[   18.824607] sp : ed5dfc70  ip : ed742d40  fp : 00000000
	[   18.824610] r10: 00000018  r9 : ed742d00  r8 : 00000000
	[   18.824613] r7 : bf26ac80  r6 : 00000000  r5 : ed155650  r4 : fffffffc
	[   18.824616] r3 : 0002f000  r2 : ffffffff  r1 : 2df30000  r0 : ed155400
	[   18.824621] Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
	[   18.824624] Control: 30c5387d  Table: aeb18840  DAC: 55555555
	[   18.824628] Process systemd-udevd (pid: 245, stack limit = 0xc66954c3)
	[   18.824633] Stack: (0xed5dfc70 to 0xed5e0000)
	[   18.824636] fc60:                                     ed155400 ed155400 00000000 c068e45c
	[   18.824641] fc80: ed155400 00000000 00000000 c06751a4 00000001 00000001 ffffffff ffffffff
	[   18.905936] fca0: ed5dfcc0 c1204c88 ed155400 00000000 00000000 00000000 bf268c5c bf1c5cd4
	[   18.914108] fcc0: ed710c08 9543847b 00000000 eea34810 00000000 bf268c5c 00000000 c06a3f64
	[   18.923651] fce0: c131dd70 eea34810 c131dd74 00000000 00000000 c06a2084 eea34810 bf268c5c
	[   18.932934] fd00: eea34844 c06a23e0 00000000 c1204c88 bf26a980 c06a22d4 eefd093c c06a23e0
	[   18.941096] fd20: 00000000 eea34810 bf268c5c eea34844 c06a23e0 00000000 c1204c88 bf26a980
	[   18.949259] fd40: 00000000 c06a24bc eea387b4 c1204c88 bf268c5c c06a038c 00000000 ee88335c
	[   18.957417] fd60: eea387b4 9543847b c1275a88 bf268c5c ed12b800 c1275a88 00000000 c06a1528
	[   18.965580] fd80: bf245be8 bf268ac8 ffffe000 bf268c5c bf268ac8 ffffe000 bf292000 c06a30d8
	[   18.973746] fda0: bf26ab80 bf268ac8 ffffe000 bf292170 c12cf160 c1204c88 ffffe000 c0202dbc
	[   18.981913] fdc0: ed667700 006000c0 c02b2844 0000000c 600d0013 bf26a980 00000040 c03650f8
	[   18.990079] fde0: a00d0013 2defd000 ee800000 006000c0 006000c0 c02b2844 0000000c c03666f4
	[   18.998244] fe00: c0358254 a00d0013 bf26a980 9543847b bf26a980 00000001 ed667700 00000001
	[   19.006404] fe20: ed1d9ee4 c02b2880 c1204c88 bf26a980 00000000 ed5dff40 00000001 ed1d9ec0
	[   19.014569] fe40: 00000001 c02b48c8 bf26a98c 00007fff bf26a980 c02b1a00 00000000 c02b1214
	[   19.022735] fe60: bf26a9c8 bf26aa80 bf26ab5c bf26aab0 c0c0387c c0e62374 c0db80fc c0db8108
	[   19.030901] fe80: c0db8160 c1204c88 bf000000 ed1296c0 06c18a20 00000000 ed1296c0 c1204c88
	[   19.039068] fea0: 00000000 00000000 00000000 00000000 00000000 00000000 6e72656b 00006c65
	[   19.047228] fec0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
	[   19.055393] fee0: 00000000 00000000 00000000 00000000 00000000 9543847b 7fffffff c1204c88
	[   19.063558] ff00: 00000000 0000000f b6c51c58 c0201204 ed5de000 0000017b bea73b0c c02b5188
	[   19.071723] ff20: 7fffffff 00000000 00000003 c0334b4c 00000002 f1bc1000 06c18a20 00000000
	[   19.079890] ff40: f1d0c3aa f1d24e80 f1bc1000 06c18a20 f87d90c0 f87d8e60 f70d7798 0016a000
	[   19.088056] ff60: 0017e730 00000000 00000000 00000000 00050ba8 00000039 0000003a 00000022
	[   19.096215] ff80: 00000000 00000013 00000000 9543847b 000000c0 00000000 b6c51c58 0000000f
	[   19.104378] ffa0: 0000017b c02011d4 00000000 b6c51c58 0000000f b6c51c58 00000000 00559220
	[   19.112543] ffc0: 00000000 b6c51c58 0000000f 0000017b 00000000 00000000 00546958 bea73b0c
	[   19.120708] ffe0: bea73af8 bea73ae8 b6c44c14 b6b4b710 600d0010 0000000f 00000000 00000000
	[   19.128884] [<c068b938>] (drm_plane_register_all) from [<c068e45c>] (drm_modeset_register_all+0xc/0x70)
	[   19.138273] [<c068e45c>] (drm_modeset_register_all) from [<c06751a4>] (drm_dev_register+0x168/0x1c4)
	[   19.147581] [<c06751a4>] (drm_dev_register) from [<bf1c5cd4>] (nouveau_platform_probe+0x6c/0x88 [nouveau])
	[   19.157434] [<bf1c5cd4>] (nouveau_platform_probe [nouveau]) from [<c06a3f64>] (platform_drv_probe+0x48/0x98)
	[   19.167256] [<c06a3f64>] (platform_drv_probe) from [<c06a2084>] (really_probe+0x1e0/0x2cc)
	[   19.175516] [<c06a2084>] (really_probe) from [<c06a22d4>] (driver_probe_device+0x60/0x16c)
	[   19.183777] [<c06a22d4>] (driver_probe_device) from [<c06a24bc>] (__driver_attach+0xdc/0xe0)
	[   19.192210] [<c06a24bc>] (__driver_attach) from [<c06a038c>] (bus_for_each_dev+0x74/0xb4)
	[   19.200383] [<c06a038c>] (bus_for_each_dev) from [<c06a1528>] (bus_add_driver+0x1c0/0x204)
	[   19.208644] [<c06a1528>] (bus_add_driver) from [<c06a30d8>] (driver_register+0x74/0x108)
	[   19.216928] [<c06a30d8>] (driver_register) from [<bf292170>] (nouveau_drm_init+0x170/0x1000 [nouveau])
	[   19.226429] [<bf292170>] (nouveau_drm_init [nouveau]) from [<c0202dbc>] (do_one_initcall+0x54/0x284)
	[   19.235557] [<c0202dbc>] (do_one_initcall) from [<c02b2880>] (do_init_module+0x64/0x214)
	[   19.243643] [<c02b2880>] (do_init_module) from [<c02b48c8>] (load_module+0x1e30/0x24a8)
	[   19.251643] [<c02b48c8>] (load_module) from [<c02b5188>] (sys_finit_module+0xc4/0xdc)
	[   19.259470] [<c02b5188>] (sys_finit_module) from [<c02011d4>] (__sys_trace_return+0x0/0x2c)
	[   19.267807] Exception stack(0xed5dffa8 to 0xed5dfff0)
	[   19.272853] ffa0:                   00000000 b6c51c58 0000000f b6c51c58 00000000 00559220
	[   19.281018] ffc0: 00000000 b6c51c58 0000000f 0000017b 00000000 00000000 00546958 bea73b0c
	[   19.289182] ffe0: bea73af8 bea73ae8 b6c44c14 b6b4b710
	[   19.294224] Code: e5b54250 e1550004 0a00000c e2444004 (e5943070)
	[   19.300863] ---[ end trace 7cb25d313b9a3b9d ]---

Fix this by initializing the mode configuration structure in the Tegra
case as well. No other modeset helper setup is required.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 drivers/gpu/drm/nouveau/nouveau_platform.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Ville Syrjälä Nov. 6, 2018, 4:41 p.m. | #1
On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Irrespective of whether or not the device has any usable outputs, the
> modesetting helpers will try to register all the resources such as CRTCs
> and planes. Unfortunately, the helpers rely on drm_mode_config_init() to
> properly set up internal data structures. Since the Tegra GPU does not
> have a display engine, the Nouveau driver doesn't set this up for Tegra,
> which results in the following oops on driver probe:

Remove DRIVER_MODESET ?

> 
> 	[   18.776221] Unable to handle kernel NULL pointer dereference at virtual address 0000006c
> 	[   18.785401] pgd = 16bb93b7
> 	[   18.789331] [0000006c] *pgd=ad58c003, *pmd=00000000
> 	[   18.800757] Internal error: Oops: 206 [#1] PREEMPT SMP ARM
> 	[   18.806233] Modules linked in: nouveau(+) ttm tegra_drm
> 	[   18.811457] CPU: 1 PID: 245 Comm: systemd-udevd Not tainted 4.20.0-rc1 #36
> 	[   18.818324] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree)
> 	[   18.824596] PC is at drm_plane_register_all+0x18/0x50
> 	[   18.824601] LR is at drm_modeset_register_all+0xc/0x70
> 	[   18.824604] pc : [<c068b938>]    lr : [<c068e45c>]    psr: a0000113
> 	[   18.824607] sp : ed5dfc70  ip : ed742d40  fp : 00000000
> 	[   18.824610] r10: 00000018  r9 : ed742d00  r8 : 00000000
> 	[   18.824613] r7 : bf26ac80  r6 : 00000000  r5 : ed155650  r4 : fffffffc
> 	[   18.824616] r3 : 0002f000  r2 : ffffffff  r1 : 2df30000  r0 : ed155400
> 	[   18.824621] Flags: NzCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
> 	[   18.824624] Control: 30c5387d  Table: aeb18840  DAC: 55555555
> 	[   18.824628] Process systemd-udevd (pid: 245, stack limit = 0xc66954c3)
> 	[   18.824633] Stack: (0xed5dfc70 to 0xed5e0000)
> 	[   18.824636] fc60:                                     ed155400 ed155400 00000000 c068e45c
> 	[   18.824641] fc80: ed155400 00000000 00000000 c06751a4 00000001 00000001 ffffffff ffffffff
> 	[   18.905936] fca0: ed5dfcc0 c1204c88 ed155400 00000000 00000000 00000000 bf268c5c bf1c5cd4
> 	[   18.914108] fcc0: ed710c08 9543847b 00000000 eea34810 00000000 bf268c5c 00000000 c06a3f64
> 	[   18.923651] fce0: c131dd70 eea34810 c131dd74 00000000 00000000 c06a2084 eea34810 bf268c5c
> 	[   18.932934] fd00: eea34844 c06a23e0 00000000 c1204c88 bf26a980 c06a22d4 eefd093c c06a23e0
> 	[   18.941096] fd20: 00000000 eea34810 bf268c5c eea34844 c06a23e0 00000000 c1204c88 bf26a980
> 	[   18.949259] fd40: 00000000 c06a24bc eea387b4 c1204c88 bf268c5c c06a038c 00000000 ee88335c
> 	[   18.957417] fd60: eea387b4 9543847b c1275a88 bf268c5c ed12b800 c1275a88 00000000 c06a1528
> 	[   18.965580] fd80: bf245be8 bf268ac8 ffffe000 bf268c5c bf268ac8 ffffe000 bf292000 c06a30d8
> 	[   18.973746] fda0: bf26ab80 bf268ac8 ffffe000 bf292170 c12cf160 c1204c88 ffffe000 c0202dbc
> 	[   18.981913] fdc0: ed667700 006000c0 c02b2844 0000000c 600d0013 bf26a980 00000040 c03650f8
> 	[   18.990079] fde0: a00d0013 2defd000 ee800000 006000c0 006000c0 c02b2844 0000000c c03666f4
> 	[   18.998244] fe00: c0358254 a00d0013 bf26a980 9543847b bf26a980 00000001 ed667700 00000001
> 	[   19.006404] fe20: ed1d9ee4 c02b2880 c1204c88 bf26a980 00000000 ed5dff40 00000001 ed1d9ec0
> 	[   19.014569] fe40: 00000001 c02b48c8 bf26a98c 00007fff bf26a980 c02b1a00 00000000 c02b1214
> 	[   19.022735] fe60: bf26a9c8 bf26aa80 bf26ab5c bf26aab0 c0c0387c c0e62374 c0db80fc c0db8108
> 	[   19.030901] fe80: c0db8160 c1204c88 bf000000 ed1296c0 06c18a20 00000000 ed1296c0 c1204c88
> 	[   19.039068] fea0: 00000000 00000000 00000000 00000000 00000000 00000000 6e72656b 00006c65
> 	[   19.047228] fec0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> 	[   19.055393] fee0: 00000000 00000000 00000000 00000000 00000000 9543847b 7fffffff c1204c88
> 	[   19.063558] ff00: 00000000 0000000f b6c51c58 c0201204 ed5de000 0000017b bea73b0c c02b5188
> 	[   19.071723] ff20: 7fffffff 00000000 00000003 c0334b4c 00000002 f1bc1000 06c18a20 00000000
> 	[   19.079890] ff40: f1d0c3aa f1d24e80 f1bc1000 06c18a20 f87d90c0 f87d8e60 f70d7798 0016a000
> 	[   19.088056] ff60: 0017e730 00000000 00000000 00000000 00050ba8 00000039 0000003a 00000022
> 	[   19.096215] ff80: 00000000 00000013 00000000 9543847b 000000c0 00000000 b6c51c58 0000000f
> 	[   19.104378] ffa0: 0000017b c02011d4 00000000 b6c51c58 0000000f b6c51c58 00000000 00559220
> 	[   19.112543] ffc0: 00000000 b6c51c58 0000000f 0000017b 00000000 00000000 00546958 bea73b0c
> 	[   19.120708] ffe0: bea73af8 bea73ae8 b6c44c14 b6b4b710 600d0010 0000000f 00000000 00000000
> 	[   19.128884] [<c068b938>] (drm_plane_register_all) from [<c068e45c>] (drm_modeset_register_all+0xc/0x70)
> 	[   19.138273] [<c068e45c>] (drm_modeset_register_all) from [<c06751a4>] (drm_dev_register+0x168/0x1c4)
> 	[   19.147581] [<c06751a4>] (drm_dev_register) from [<bf1c5cd4>] (nouveau_platform_probe+0x6c/0x88 [nouveau])
> 	[   19.157434] [<bf1c5cd4>] (nouveau_platform_probe [nouveau]) from [<c06a3f64>] (platform_drv_probe+0x48/0x98)
> 	[   19.167256] [<c06a3f64>] (platform_drv_probe) from [<c06a2084>] (really_probe+0x1e0/0x2cc)
> 	[   19.175516] [<c06a2084>] (really_probe) from [<c06a22d4>] (driver_probe_device+0x60/0x16c)
> 	[   19.183777] [<c06a22d4>] (driver_probe_device) from [<c06a24bc>] (__driver_attach+0xdc/0xe0)
> 	[   19.192210] [<c06a24bc>] (__driver_attach) from [<c06a038c>] (bus_for_each_dev+0x74/0xb4)
> 	[   19.200383] [<c06a038c>] (bus_for_each_dev) from [<c06a1528>] (bus_add_driver+0x1c0/0x204)
> 	[   19.208644] [<c06a1528>] (bus_add_driver) from [<c06a30d8>] (driver_register+0x74/0x108)
> 	[   19.216928] [<c06a30d8>] (driver_register) from [<bf292170>] (nouveau_drm_init+0x170/0x1000 [nouveau])
> 	[   19.226429] [<bf292170>] (nouveau_drm_init [nouveau]) from [<c0202dbc>] (do_one_initcall+0x54/0x284)
> 	[   19.235557] [<c0202dbc>] (do_one_initcall) from [<c02b2880>] (do_init_module+0x64/0x214)
> 	[   19.243643] [<c02b2880>] (do_init_module) from [<c02b48c8>] (load_module+0x1e30/0x24a8)
> 	[   19.251643] [<c02b48c8>] (load_module) from [<c02b5188>] (sys_finit_module+0xc4/0xdc)
> 	[   19.259470] [<c02b5188>] (sys_finit_module) from [<c02011d4>] (__sys_trace_return+0x0/0x2c)
> 	[   19.267807] Exception stack(0xed5dffa8 to 0xed5dfff0)
> 	[   19.272853] ffa0:                   00000000 b6c51c58 0000000f b6c51c58 00000000 00559220
> 	[   19.281018] ffc0: 00000000 b6c51c58 0000000f 0000017b 00000000 00000000 00546958 bea73b0c
> 	[   19.289182] ffe0: bea73af8 bea73ae8 b6c44c14 b6b4b710
> 	[   19.294224] Code: e5b54250 e1550004 0a00000c e2444004 (e5943070)
> 	[   19.300863] ---[ end trace 7cb25d313b9a3b9d ]---
> 
> Fix this by initializing the mode configuration structure in the Tegra
> case as well. No other modeset helper setup is required.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  drivers/gpu/drm/nouveau/nouveau_platform.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c
> index 039e23548e08..1d4c895b379d 100644
> --- a/drivers/gpu/drm/nouveau/nouveau_platform.c
> +++ b/drivers/gpu/drm/nouveau/nouveau_platform.c
> @@ -34,6 +34,8 @@ static int nouveau_platform_probe(struct platform_device *pdev)
>  	if (IS_ERR(drm))
>  		return PTR_ERR(drm);
>  
> +	drm_mode_config_init(drm);
> +
>  	ret = drm_dev_register(drm, 0);
>  	if (ret < 0) {
>  		drm_dev_put(drm);
> @@ -46,7 +48,10 @@ static int nouveau_platform_probe(struct platform_device *pdev)
>  static int nouveau_platform_remove(struct platform_device *pdev)
>  {
>  	struct drm_device *dev = platform_get_drvdata(pdev);
> +
> +	drm_mode_config_cleanup(dev);
>  	nouveau_drm_device_remove(dev);
> +
>  	return 0;
>  }
>  
> -- 
> 2.19.1
> 
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
Thierry Reding Nov. 7, 2018, 3:34 p.m. | #2
On Tue, Nov 06, 2018 at 06:41:22PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Irrespective of whether or not the device has any usable outputs, the
> > modesetting helpers will try to register all the resources such as CRTCs
> > and planes. Unfortunately, the helpers rely on drm_mode_config_init() to
> > properly set up internal data structures. Since the Tegra GPU does not
> > have a display engine, the Nouveau driver doesn't set this up for Tegra,
> > which results in the following oops on driver probe:
> 
> Remove DRIVER_MODESET ?

Yeah, that works as well. Technically I suppose somebody could be
instantiating the IP in an SoC and include a display engine, in which
case we'd need the DRIVER_MODESET feature again, but I'm not aware of
anyone doing that, so it may not be worth planning for that at this
point.

Thierry
Ilia Mirkin Nov. 7, 2018, 3:52 p.m. | #3
On Wed, Nov 7, 2018 at 10:34 AM Thierry Reding <thierry.reding@gmail.com> wrote:
>
> On Tue, Nov 06, 2018 at 06:41:22PM +0200, Ville Syrjälä wrote:
> > On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > >
> > > Irrespective of whether or not the device has any usable outputs, the
> > > modesetting helpers will try to register all the resources such as CRTCs
> > > and planes. Unfortunately, the helpers rely on drm_mode_config_init() to
> > > properly set up internal data structures. Since the Tegra GPU does not
> > > have a display engine, the Nouveau driver doesn't set this up for Tegra,
> > > which results in the following oops on driver probe:
> >
> > Remove DRIVER_MODESET ?
>
> Yeah, that works as well. Technically I suppose somebody could be
> instantiating the IP in an SoC and include a display engine, in which
> case we'd need the DRIVER_MODESET feature again, but I'm not aware of
> anyone doing that, so it may not be worth planning for that at this
> point.

I thought DRIVER_MODESET was required even for rendernodes. Is that no
longer the case?

Note that e.g. GF117 GPUs also don't have a display engine hooked up
in nouveau (or in hardware).

  -ilia
Thierry Reding Nov. 7, 2018, 4:12 p.m. | #4
On Wed, Nov 07, 2018 at 10:52:11AM -0500, Ilia Mirkin wrote:
> On Wed, Nov 7, 2018 at 10:34 AM Thierry Reding <thierry.reding@gmail.com> wrote:
> >
> > On Tue, Nov 06, 2018 at 06:41:22PM +0200, Ville Syrjälä wrote:
> > > On Tue, Nov 06, 2018 at 05:24:15PM +0100, Thierry Reding wrote:
> > > > From: Thierry Reding <treding@nvidia.com>
> > > >
> > > > Irrespective of whether or not the device has any usable outputs, the
> > > > modesetting helpers will try to register all the resources such as CRTCs
> > > > and planes. Unfortunately, the helpers rely on drm_mode_config_init() to
> > > > properly set up internal data structures. Since the Tegra GPU does not
> > > > have a display engine, the Nouveau driver doesn't set this up for Tegra,
> > > > which results in the following oops on driver probe:
> > >
> > > Remove DRIVER_MODESET ?
> >
> > Yeah, that works as well. Technically I suppose somebody could be
> > instantiating the IP in an SoC and include a display engine, in which
> > case we'd need the DRIVER_MODESET feature again, but I'm not aware of
> > anyone doing that, so it may not be worth planning for that at this
> > point.
> 
> I thought DRIVER_MODESET was required even for rendernodes. Is that no
> longer the case?

Indeed. Removing the DRIVER_MODESET feature gets the driver to load
properly, but trying to actually use Nouveau (e.g. kmscube) crashes
in other places.

Now that you mention it, I vaguely remember trying to do something
similar a long time ago and I had to split up DRIVER_MODESET into more
fine-grained features (basically DRIVER_MODESET and DRIVER_LEGACY, if
I remember correctly) to avoid crashes. But this must have been three
or four years ago and I can't recall the exact details.

> Note that e.g. GF117 GPUs also don't have a display engine hooked up
> in nouveau (or in hardware).

That's interesting. I think there'd be some symmetric elegance to it if
the PCI driver supported DRIVER_MODESET irrespective of the feature set
of the card and if the platform driver did the same. In the end, this
isn't really a driver-specific feature, but a device-specific feature.
Or to put it another way: the driver inherently supports modesetting
features, irrespective of a device's specific capabilities.

Thierry

Patch

diff --git a/drivers/gpu/drm/nouveau/nouveau_platform.c b/drivers/gpu/drm/nouveau/nouveau_platform.c
index 039e23548e08..1d4c895b379d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_platform.c
+++ b/drivers/gpu/drm/nouveau/nouveau_platform.c
@@ -34,6 +34,8 @@  static int nouveau_platform_probe(struct platform_device *pdev)
 	if (IS_ERR(drm))
 		return PTR_ERR(drm);
 
+	drm_mode_config_init(drm);
+
 	ret = drm_dev_register(drm, 0);
 	if (ret < 0) {
 		drm_dev_put(drm);
@@ -46,7 +48,10 @@  static int nouveau_platform_probe(struct platform_device *pdev)
 static int nouveau_platform_remove(struct platform_device *pdev)
 {
 	struct drm_device *dev = platform_get_drvdata(pdev);
+
+	drm_mode_config_cleanup(dev);
 	nouveau_drm_device_remove(dev);
+
 	return 0;
 }