From patchwork Wed Jun 8 08:24:47 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [5/6] target-i386: Make x86 mfence and lfence illegal without SSE2 From: Stefan Hajnoczi X-Patchwork-Id: 99377 Message-Id: <1307521488-6066-6-git-send-email-stefanha@linux.vnet.ibm.com> To: Cc: Martin Simmons , Stefan Hajnoczi Date: Wed, 8 Jun 2011 09:24:47 +0100 From: Martin Simmons While trying to use qemu -cpu pentium3 to test for incorrect uses of certain SSE2 instructions, I found that QEMU allowed the mfence and lfence instructions to be executed even though Pentium 3 doesn't support them. According to the processor specs (and experience on a real Pentium 3), these instructions are only available with SSE2, but QEMU is checking for SSE. The check for the related sfence instruction is correct (it works with SSE). This trival patch fixes the test. Signed-off-by: Martin Simmons Signed-off-by: Stefan Hajnoczi --- target-i386/translate.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index 199302e..10bd72a 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7538,7 +7538,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) break; case 5: /* lfence */ case 6: /* mfence */ - if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE)) + if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2)) goto illegal_op; break; case 7: /* sfence / clflush */