From patchwork Wed Oct 31 23:48:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Reddy X-Patchwork-Id: 991750 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="gsxY4EYg"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42llRT1fmKz9s1c for ; Thu, 1 Nov 2018 10:49:09 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728738AbeKAItZ (ORCPT ); Thu, 1 Nov 2018 04:49:25 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:7377 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725755AbeKAItY (ORCPT ); Thu, 1 Nov 2018 04:49:24 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 31 Oct 2018 16:48:44 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 31 Oct 2018 16:48:59 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 31 Oct 2018 16:48:59 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 31 Oct 2018 23:48:59 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Wed, 31 Oct 2018 23:48:59 +0000 Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 31 Oct 2018 16:48:59 -0700 From: Krishna Reddy To: , , CC: , , , , , , , , , , , Krishna Reddy Subject: [PATCH v2 5/5] arm64: tegra: Add SMMU nodes to Tegra194 device tree Date: Wed, 31 Oct 2018 16:48:36 -0700 Message-ID: <1541029716-14353-6-git-send-email-vdumpa@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1541029716-14353-2-git-send-email-vdumpa@nvidia.com> References: <1541029716-14353-2-git-send-email-vdumpa@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1541029724; bh=uy23Uk6hkXDsgDDR2KU6VDMh50jPeYD/iv4dZnDF8mg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=gsxY4EYgtUVVPBOmhzQ9uSxFYPxzzf83bn9QxPf158aWiXBZv86HQ72VYgzll6yuN m6sE3mrQkv7ViMInpkiQMBDuxntbNDyurgPkF2BrnJrmfW22rQWwtvutZ/VpxR2uBB rCG2tSwTK1612xOxj0T+gesdMSsEBIS1d3l1ztbuoGBSeaqI+ASgB5O+VqUOMtn8An kbtLxcu2Orlro/0Szk0RFOHSJobDnNFvk1NeduSYnl46hKfXtdjhCi/512AQC3d2Bg JpFv36t+OIS7Ch1IrlW7vQQGv/MX+4Y1RiIEqQKFCzBnQsQhnzNB8uk1Acz0NLid8w 5Zoj8wxmmrEPw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add SMMU nodes and dma-ranges to Tegra194 device tree. Tegra194 has three ARM SMMU Instances. Two of them are used together to access IOVA interleaved. The third one is used as regular ARM SMMU. Signed-off-by: Krishna Reddy --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 148 +++++++++++++++++++++++++++++++ 1 file changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 9fc14bb..03fe2b4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -10,6 +10,7 @@ interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; + dma-ranges = <0x0 0x0 0x0 0x0 0x8 0x0>; /* control backbone */ cbb { @@ -447,4 +448,151 @@ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; interrupt-parent = <&gic>; }; + + dualsmmu: iommu@12000000 { + compatible = "tegra194,arm,mmu-500"; + reg = <0 0x12000000 0 0x800000>, + <0 0x11000000 0 0x800000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + }; + + smmu: iommu@10000000 { + compatible = "arm,mmu-500"; + reg = <0 0x10000000 0 0x800000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + stream-match-mask = <0x7f80>; + #global-interrupts = <1>; + #iommu-cells = <1>; + }; };