diff mbox series

[Bionic,09/18] powerpc/powernv/ioda2: Reduce upper limit for DMA window size

Message ID 20181031150931.16284-10-joserz@linux.ibm.com
State New
Headers show
Series NVIDIA GPU passthrough - part I | expand

Commit Message

Jose Ricardo Ziviani Oct. 31, 2018, 3:09 p.m. UTC 
From: Alexey Kardashevskiy <aik@ozlabs.ru>

BugLink: https://bugs.launchpad.net/qemu-kvm/+bug/1800649

We use PHB in mode1 which uses bit 59 to select a correct DMA window.
However there is mode2 which uses bits 59:55 and allows up to 32 DMA
windows per a PE.

Even though documentation does not clearly specify that, it seems that
the actual hardware does not support bits 59:55 even in mode1, in other
words we can create a window as big as 1<<58 but DMA simply won't work.

This reduces the upper limit from 59 to 55 bits to let the userspace know
about the hardware limits.

Fixes: 7aafac11e3 "powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested"
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
(cherry picked from commit d3d4ffaae439981e1e441ebb125aa3588627c5d8)
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.ibm.com>
---
 arch/powerpc/platforms/powernv/pci-ioda.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index f0cdb4667f44..bd0c5950b84d 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
@@ -2832,7 +2832,7 @@  static long pnv_pci_ioda2_table_alloc_pages(int nid, __u64 bus_offset,
 	level_shift = entries_shift + 3;
 	level_shift = max_t(unsigned, level_shift, PAGE_SHIFT);
 
-	if ((level_shift - 3) * levels + page_shift >= 60)
+	if ((level_shift - 3) * levels + page_shift >= 55)
 		return -EINVAL;
 
 	/* Allocate TCE table */