From patchwork Mon Oct 29 06:19:07 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rashmica Gupta X-Patchwork-Id: 990064 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42k4FD6D5Vz9s7h for ; Mon, 29 Oct 2018 17:19:28 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OXQqk64E"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42k4FD35slzDrcP for ; Mon, 29 Oct 2018 17:19:28 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OXQqk64E"; dkim-atps=neutral X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::544; helo=mail-pg1-x544.google.com; envelope-from=rashmica.g@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="OXQqk64E"; dkim-atps=neutral Received: from mail-pg1-x544.google.com (mail-pg1-x544.google.com [IPv6:2607:f8b0:4864:20::544]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42k4F55N8szDrYb for ; Mon, 29 Oct 2018 17:19:21 +1100 (AEDT) Received: by mail-pg1-x544.google.com with SMTP id w3-v6so3357420pgs.11 for ; Sun, 28 Oct 2018 23:19:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=vscWZWl61fHvGCDNx3Gh3qhSuCaFZTtzdA9b51nIVtk=; b=OXQqk64EQRfANqRklbvYGamnTHJomSO97ZFVGhifeAgIniqappq7Cwy1rX0zUYgibJ si9+AB+skmX+r+i6yQa1FGWbWCMJy2mg03Sy8N841lre8UZ5QEkO95RqvPpauMYCJpm/ 2rog0o5WDfFApInVpZVT4ERlsYg/02tD+VmfhLtk0IYEspBFQwLX8TEOTxG+HGqWcPA/ HA0IveYFI08+3S+QuY8caheVBWa9r1XW1tiUuzocCI/NxlpTsh3X8/PgO1DgEm5I8eYn gGfJH68YGmB7a2OJlTmYjnPZtQ6FHif7k2Tsn/1VMVEboJb81ts4N84KEbgoByuzCfbm HXEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=vscWZWl61fHvGCDNx3Gh3qhSuCaFZTtzdA9b51nIVtk=; b=HWNvALd5ixmszKfP4NV2Cqyexs+PoPr6FyfEoxNXw9G6efgRczH5qSoZrbG4tBiYwh rZEB9JoGpWGw2Rh37lEOO+XgrLxaM4jzXUhaBWRR0ObCPf845OtwsPssrSzw9WNU4Y2M hc+Xq9pP67OyILLk+j6t4DM2U1Vq/GpRfYfg5RGJufj/TB6zbxm7bC0N7+Ahqno4F0eZ FsthTSfy/jIpdIZa0vPsO8k3ASvNDx0J8GfOqZd3FLNa/nCXnwvSU/GkBwPTHkVP8NR/ DOGWV2mDbAKjmCK+EEWSGr7r1FkQ0vFEcpEEeQJU4IIlAdaLIoUttNe+mRXG9/1pSSln aBTA== X-Gm-Message-State: AGRZ1gJ+6NLmOADLjX1BCN65cmaAoepHtHq85CG66liOoQPEMEybDlPH nbhx7FFFxCpvkGOFUhpIk4Zcoe5+ X-Google-Smtp-Source: AJdET5cZDfV6laMhMn8K+bqxL/QYWph1JsjZ9mDRdcuk7sp9IzPbBCMbxk3Uu/oecMphfZQQmo6OhA== X-Received: by 2002:a62:3301:: with SMTP id z1-v6mr13587105pfz.85.1540793958955; Sun, 28 Oct 2018 23:19:18 -0700 (PDT) Received: from rashmica.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id d65-v6sm12836714pfm.100.2018.10.28.23.19.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 28 Oct 2018 23:19:18 -0700 (PDT) From: Rashmica Gupta To: skiboot@lists.ozlabs.org Date: Mon, 29 Oct 2018 17:19:07 +1100 Message-Id: <20181029061907.31951-1-rashmica.g@gmail.com> X-Mailer: git-send-email 2.17.2 Subject: [Skiboot] [PATCH] Add in new OPAL call to flush the L2 and L3 caches. X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair@popple.id.au MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Using the dcbf instruction is really slow... This is much faster. Suggested-by: Alistair Popple Signed-off-by: Rashmica Gupta --- Stewart: I realise that cpu.c is probably not where this should live... Thoughts on where it should go? Context: When resetting a GPU we want to make sure all dirty cache lines in the CPU cache are cleared. Hit up Alexey and Alistair for the nitty gritty details. core/cpu.c | 108 +++++++++++++++++++++++++++++++++++++++++++++ include/cpu.h | 2 + include/opal-api.h | 3 +- 3 files changed, 112 insertions(+), 1 deletion(-) diff --git a/core/cpu.c b/core/cpu.c index 4f518a4c..bc4fcaf8 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -1630,3 +1630,111 @@ static int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr) return rc; } opal_call(OPAL_NMMU_SET_PTCR, opal_nmmu_set_ptcr, 2); + + +#define L2_PRD_PURGE_CMD_REG 0x1080E +#define L2_PRD_PURGE_CMD_REG_BUSY 0x0040000000000000 +#define L2_PRD_PURGE_CMD_TRIGGER 0x8000000000000000 +#define L3_PRD_PURGE_REG 0x1180E +#define L3_PRD_PURGE_REQ 0x8000000000000000 +#define TIMEOUT_MS 2 + +static inline bool time_expired(unsigned long start) +{ + unsigned long time = tb_to_msecs(mftb()); + + if (time - start > TIMEOUT_MS) { + return true; + } + return false; +} + +static int flush_l2_caches(uint32_t chip_id, uint32_t core_id) +{ + int rc, timeout = 0; + unsigned long start_time; + uint64_t val = L2_PRD_PURGE_CMD_REG_BUSY; + uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L2_PRD_PURGE_CMD_REG); + + rc = xscom_write_mask(chip_id, addr, L2_PRD_PURGE_CMD_TRIGGER, + L2_PRD_PURGE_CMD_TRIGGER); + if (rc) { + prlog(PR_ERR, "FLUSH L2 on core 0x%x: XSCOM write_mask failed %i\n", core_id, rc); + } + start_time = tb_to_msecs(mftb()); + while ((val & L2_PRD_PURGE_CMD_REG_BUSY) && !(timeout = time_expired(start_time))) { + rc = xscom_read(chip_id, addr, &val); + if (rc) { + prlog(PR_ERR, "FLUSH L2 on core 0x%x: XSCOM read failed %i\n", core_id, rc); + break; + } + } + if (timeout) { + prlog(PR_ERR, "FLUSH L3 on core 0x%x timed out %i\n", core_id, rc); + return OPAL_BUSY; + } + + /* We have to clear the trigger bit ourselves */ + val &= ~L2_PRD_PURGE_CMD_TRIGGER; + rc = xscom_write(chip_id, addr, val); + if (rc) + prlog(PR_ERR, "FLUSH L2 on core 0x%x: XSCOM write failed %i\n", core_id, rc); + return 0; + +} + +static int flush_l3_caches(uint32_t chip_id, uint32_t core_id) +{ + int rc, timeout = 0; + unsigned long start_time; + uint64_t val = L3_PRD_PURGE_REQ; + uint64_t addr = XSCOM_ADDR_P9_EX(core_id, L3_PRD_PURGE_REG); + + rc = xscom_write_mask(chip_id, addr, L3_PRD_PURGE_REQ, L3_PRD_PURGE_REQ); + if (rc) { + prlog(PR_ERR, "FLUSH L3 on core 0x%x: XSCOM write_mask failed %i\n", core_id, rc); + } + + /* Trigger bit is automatically set to zero when flushing is done*/ + start_time = tb_to_msecs(mftb()); + while ((val & L3_PRD_PURGE_REQ) && !(timeout = time_expired(start_time) )) { + rc = xscom_read(chip_id, addr, &val); + if (rc) { + prlog(PR_ERR, "FLUSH L3 on core 0x%x: XSCOM read failed %i\n", core_id, rc); + break; + } + } + if (timeout) { + prlog(PR_ERR, "FLUSH L3 on core 0x%x timed out %i\n", core_id, rc); + return OPAL_BUSY; + } + + return 0; +} + +int flush_caches(void) +{ + int rc = 0; + struct cpu_thread *t; + uint64_t chip_id, core_id, prev_core_id = 0xdeadbeef; + + if ((mfspr(SPR_PVR) & PVR_TYPE_P9) != PVR_TYPE_P9) + return OPAL_UNSUPPORTED; + + for_each_cpu(t) { + /* Only need to do it once per core chiplet */ + core_id = pir_to_core_id(t->pir); + if (prev_core_id == core_id) + continue; + prev_core_id = core_id; + chip_id = t->chip_id; + + rc |= flush_l2_caches(chip_id, core_id); + rc |= flush_l3_caches(chip_id, core_id); + } + + return rc; +} + + +opal_call(OPAL_CLEAR_CACHE, flush_caches, 0); diff --git a/include/cpu.h b/include/cpu.h index 2fe47982..04c862c5 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -329,4 +329,6 @@ int dctl_set_special_wakeup(struct cpu_thread *t); int dctl_clear_special_wakeup(struct cpu_thread *t); int dctl_core_is_gated(struct cpu_thread *t); +extern int flush_caches(void); + #endif /* __CPU_H */ diff --git a/include/opal-api.h b/include/opal-api.h index 5f397c8e..c24838d2 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -226,7 +226,8 @@ #define OPAL_NX_COPROC_INIT 167 #define OPAL_NPU_SET_RELAXED_ORDER 168 #define OPAL_NPU_GET_RELAXED_ORDER 169 -#define OPAL_LAST 169 +#define OPAL_CLEAR_CACHE 170 +#define OPAL_LAST 170 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */