diff mbox series

[rs6000] Add __ieee128 argument support to the scalar_cmp_exp family of builtins

Message ID 1540410263.3794.7.camel@us.ibm.com
State New
Headers show
Series [rs6000] Add __ieee128 argument support to the scalar_cmp_exp family of builtins | expand

Commit Message

Carl Love Oct. 24, 2018, 7:44 p.m. UTC 
GCC Maintainers:

The scalar_cmp_exp_eq, scalar_cmp_lt, scalar_cmp_gt,
scalar_cmp_unordered are missing support for the _ieee128 arguments. 
This patch adds the missing support and a test file for the builtins
for both _ieee128 and double arguments.

I have tested the attached patch on

 powerpc64le-unknown-linux-gnu (Power 8 LE),   
 powerpc64le-unknown-linux-gnu (Power 9 LE) 

with no regressions.

Please let me know if the following patch is acceptable.  Thanks.

                       Carl Love

--------------------------------------------------------------------


gcc/ChangeLog:

2018-10-24  Carl Love  <cel@us.ibm.com>

	* config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_VSCEDPGT,
	P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VEC_VSCEDPEQ,
	P9V_BUILTIN_VEC_VSCEDPUO): Rename base overloaded name.  Add quad
	precicion entry for each overloaded builtin.
	* config/rs6000/rs6000-builtin.def (VSCEDPGT, VSCEDPLT,	VSCEDPEQ,
	VSCEDPUO): Rename overloaded name.
	(VSCEDPGT, VSCEQPGT, VSCEDPLT, VSCEQPLT, VSCEDPEQ, VSCEQPEQ,
	VSCEDPUO, VSCEQPUO): Add defitions for overloaded builtins.
	* config/rs6000/vsx.md (xscmpexpqp_<code>_<mode>, *xscmpexpqp): Add
	define_expand and define_insn for the instructions for the new builtins.

gcc/testsuite/ChangeLog:

2018-10-24  Carl Love  <cel@us.ibm.com>

	* gcc.target/powerpc/float128-cmp2-runnable.c: New test file.
---
 gcc/config/rs6000/rs6000-builtin.def          |  21 +-
 gcc/config/rs6000/rs6000-c.c                  |  16 +-
 gcc/config/rs6000/vsx.md                      |  29 ++
 .../powerpc/float128-cmp2-runnable.c          | 278 ++++++++++++++++++
 4 files changed, 336 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c

-- 
2.17.1

Comments

Segher Boessenkool Oct. 25, 2018, 7:21 p.m. UTC | #1 
Hi Carl,

On Wed, Oct 24, 2018 at 12:44:23PM -0700, Carl Love wrote:
> The scalar_cmp_exp_eq, scalar_cmp_lt, scalar_cmp_gt,
> scalar_cmp_unordered are missing support for the _ieee128 arguments. 
> This patch adds the missing support and a test file for the builtins
> for both _ieee128 and double arguments.

> 	* config/rs6000/rs6000-c.c (P9V_BUILTIN_VEC_VSCEDPGT,
> 	P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VEC_VSCEDPEQ,
> 	P9V_BUILTIN_VEC_VSCEDPUO): Rename base overloaded name.  Add quad
> 	precicion entry for each overloaded builtin.
> 	* config/rs6000/rs6000-builtin.def (VSCEDPGT, VSCEDPLT,	VSCEDPEQ,

There's a stray tab in this last line.

> 	VSCEDPUO): Rename overloaded name.
> 	(VSCEDPGT, VSCEQPGT, VSCEDPLT, VSCEQPLT, VSCEDPEQ, VSCEQPEQ,
> 	VSCEDPUO, VSCEQPUO): Add defitions for overloaded builtins.
> 	* config/rs6000/vsx.md (xscmpexpqp_<code>_<mode>, *xscmpexpqp): Add
> 	define_expand and define_insn for the instructions for the new builtins.

Make separate entries in the changelog for the expand and the insn please.

> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c
> @@ -0,0 +1,278 @@
> +/* { dg-do run { target { powerpc*-*-* && { lp64 && p9vector_hw } } } } */

Does this need lp64?  p9vector_hw implies lp64 of course, so it won't
make any difference.

> +/* { dg-require-effective-target powerpc_p9vector_ok } */

Is this not implied by p9vector_hw?

Okay for trunk with those things tuned a bit.  Thanks!


Segher
diff mbox series

Patch

diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def
index ec0528a7a..ac695b6ed 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -2117,6 +2117,11 @@  BU_P9V_VSX_2 (VSCEDPLT,	"scalar_cmp_exp_dp_lt",	CONST,	xscmpexpdp_lt)
 BU_P9V_VSX_2 (VSCEDPEQ,	"scalar_cmp_exp_dp_eq",	CONST,	xscmpexpdp_eq)
 BU_P9V_VSX_2 (VSCEDPUO,	"scalar_cmp_exp_dp_unordered",	CONST,	xscmpexpdp_unordered)
 
+BU_P9V_VSX_2 (VSCEQPGT,	"scalar_cmp_exp_qp_gt",	CONST,	xscmpexpqp_gt_kf)
+BU_P9V_VSX_2 (VSCEQPLT,	"scalar_cmp_exp_qp_lt",	CONST,	xscmpexpqp_lt_kf)
+BU_P9V_VSX_2 (VSCEQPEQ,	"scalar_cmp_exp_qp_eq",	CONST,	xscmpexpqp_eq_kf)
+BU_P9V_VSX_2 (VSCEQPUO,	"scalar_cmp_exp_qp_unordered",	CONST,	xscmpexpqp_unordered_kf)
+
 BU_FLOAT128_HW_VSX_2 (VSTDCQP, "scalar_test_data_class_qp",	CONST,	xststdcqp_kf)
 BU_P9V_VSX_2 (VSTDCDP,	"scalar_test_data_class_dp",	CONST,	xststdcdp)
 BU_P9V_VSX_2 (VSTDCSP,	"scalar_test_data_class_sp",	CONST,	xststdcsp)
@@ -2146,10 +2151,18 @@  BU_P9V_OVERLOAD_2 (VSTDCQP,	"scalar_test_data_class_qp")
 BU_P9V_OVERLOAD_2 (VSTDCDP,	"scalar_test_data_class_dp")
 BU_P9V_OVERLOAD_2 (VSTDCSP,	"scalar_test_data_class_sp")
 
-BU_P9V_OVERLOAD_2 (VSCEDPGT,	"scalar_cmp_exp_gt")
-BU_P9V_OVERLOAD_2 (VSCEDPLT,	"scalar_cmp_exp_lt")
-BU_P9V_OVERLOAD_2 (VSCEDPEQ,	"scalar_cmp_exp_eq")
-BU_P9V_OVERLOAD_2 (VSCEDPUO,	"scalar_cmp_exp_unordered")
+BU_P9V_OVERLOAD_2 (VSCEGT,	"scalar_cmp_exp_gt")
+BU_P9V_OVERLOAD_2 (VSCEDPGT,	"scalar_cmp_exp_dp_gt")
+BU_P9V_OVERLOAD_2 (VSCEQPGT,	"scalar_cmp_exp_qp_gt")
+BU_P9V_OVERLOAD_2 (VSCELT,	"scalar_cmp_exp_lt")
+BU_P9V_OVERLOAD_2 (VSCEDPLT,	"scalar_cmp_exp_dp_lt")
+BU_P9V_OVERLOAD_2 (VSCEQPLT,	"scalar_cmp_exp_qp_lt")
+BU_P9V_OVERLOAD_2 (VSCEEQ,	"scalar_cmp_exp_eq")
+BU_P9V_OVERLOAD_2 (VSCEDPEQ,	"scalar_cmp_exp_dp_eq")
+BU_P9V_OVERLOAD_2 (VSCEQPEQ,	"scalar_cmp_exp_qp_eq")
+BU_P9V_OVERLOAD_2 (VSCEUO,	"scalar_cmp_exp_unordered")
+BU_P9V_OVERLOAD_2 (VSCEDPUO,	"scalar_cmp_exp_dp_unordered")
+BU_P9V_OVERLOAD_2 (VSCEQPUO,	"scalar_cmp_exp_qp_unordered")
 
 /* 1 argument vsx vector functions added in ISA 3.0 (power9).  */
 BU_P9V_VSX_1 (VEEDP, "extract_exp_dp", CONST, xvxexpdp)
diff --git a/gcc/config/rs6000/rs6000-c.c b/gcc/config/rs6000/rs6000-c.c
index 4d5e3c226..c3586b0df 100644
--- a/gcc/config/rs6000/rs6000-c.c
+++ b/gcc/config/rs6000/rs6000-c.c
@@ -5061,14 +5061,22 @@  const struct altivec_builtin_types altivec_overloaded_builtins[] = {
   { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF,
     RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 },
 
-  { P9V_BUILTIN_VEC_VSCEDPGT, P9V_BUILTIN_VSCEDPGT,
+  { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT,
     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
-  { P9V_BUILTIN_VEC_VSCEDPLT, P9V_BUILTIN_VSCEDPLT,
+  { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT,
+    RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
+  { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT,
     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
-  { P9V_BUILTIN_VEC_VSCEDPEQ, P9V_BUILTIN_VSCEDPEQ,
+  { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT,
+    RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
+  { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ,
     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
-  { P9V_BUILTIN_VEC_VSCEDPUO, P9V_BUILTIN_VSCEDPUO,
+  { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ,
+    RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
+  { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO,
     RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 },
+  { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO,
+    RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 },
 
   { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R,
     RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI,
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index e296be96f..13842cb53 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -381,6 +381,7 @@ 
    UNSPEC_VSX_SIEXPDP
    UNSPEC_VSX_SIEXPQP
    UNSPEC_VSX_SCMPEXPDP
+   UNSPEC_VSX_SCMPEXPQP
    UNSPEC_VSX_STSTDC
    UNSPEC_VSX_VEXTRACT_FP_FROM_SHORTH
    UNSPEC_VSX_VEXTRACT_FP_FROM_SHORTL
@@ -4560,6 +4561,34 @@ 
   "xscmpexpdp %0,%x1,%x2"
   [(set_attr "type" "fpcompare")])
 
+;; VSX Scalar Compare Exponents Quad-Precision
+(define_expand "xscmpexpqp_<code>_<mode>"
+  [(set (match_dup 3)
+	(compare:CCFP
+	 (unspec:IEEE128
+	  [(match_operand:IEEE128 1 "vsx_register_operand" "v")
+	   (match_operand:IEEE128 2 "vsx_register_operand" "v")]
+	  UNSPEC_VSX_SCMPEXPQP)
+	 (const_int 0)))
+   (set (match_operand:SI 0 "register_operand" "=r")
+	(CMP_TEST:SI (match_dup 3)
+		     (const_int 0)))]
+  "TARGET_P9_VECTOR"
+{
+  operands[3] = gen_reg_rtx (CCFPmode);
+})
+
+(define_insn "*xscmpexpqp"
+  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
+	(compare:CCFP
+	 (unspec:IEEE128 [(match_operand:IEEE128 1 "altivec_register_operand" "v")
+		          (match_operand:IEEE128 2 "altivec_register_operand" "v")]
+	  UNSPEC_VSX_SCMPEXPQP)
+	 (match_operand:SI 3 "zero_constant" "j")))]
+  "TARGET_P9_VECTOR"
+  "xscmpexpqp %0,%1,%2"
+  [(set_attr "type" "fpcompare")])
+
 ;; VSX Scalar Test Data Class Quad-Precision
 ;;  (Expansion for scalar_test_data_class (__ieee128, int))
 ;;   (Has side effect of setting the lt bit if operand 1 is negative,
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c
new file mode 100644
index 000000000..59503e499
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/float128-cmp2-runnable.c
@@ -0,0 +1,278 @@ 
+/* { dg-do run { target { powerpc*-*-* && { lp64 && p9vector_hw } } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-O2 -mcpu=power9 " } */
+
+#define NAN_Q __builtin_nanq ("")
+#define SNAN_Q __builtin_nansq ("")
+#define NAN __builtin_nan ("")
+#define SNAN __builtin_nans ("")
+
+#ifdef DEBUG
+#include <stdio.h>
+#endif
+
+void abort (void);
+
+int main(void)
+{
+  int result;
+  double a_dble, b_dble;
+  __ieee128 a_ieee128, b_ieee128;
+  
+  a_dble = 3.10;
+  b_dble = 3.10;
+  
+  if (__builtin_vec_scalar_cmp_exp_eq(a_dble, b_dble))
+#ifdef DEBUG
+    printf("Double EQ result is true, expecting true\n");
+#else
+    ;
+#endif
+  else
+#ifdef DEBUG
+    printf("ERROR: Double EQ result is false, expecting true\n");
+#else
+    abort();
+#endif
+
+  a_dble = 3.10;
+  b_dble = 31.0;
+  
+  if (__builtin_vec_scalar_cmp_exp_eq(a_dble, b_dble))
+#ifdef DEBUG
+    printf("ERROR: Double EQ result is true, expecting false\n");
+#else
+    abort();
+#endif
+  else
+#ifdef DEBUG
+    printf("Double EQ result is false, expecting false\n");
+#else
+    ;
+#endif
+
+  a_dble = 3.10;
+  b_dble = 3.10;
+
+  if (__builtin_vec_scalar_cmp_exp_lt(a_dble, b_dble))
+#ifdef DEBUG
+    printf("ERROR: Double LT result is true, expecting false\n");
+#else
+    abort();
+#endif
+  else
+#ifdef DEBUG
+    printf("Double LT result is false, expecting false\n");
+#else
+    ;
+#endif
+
+  a_dble = 0.31;
+  b_dble = 3.10;
+  
+  if (__builtin_vec_scalar_cmp_exp_lt(a_dble, b_dble))
+#ifdef DEBUG
+    printf("Double LT result is true, expecting true\n");
+#else
+    ;
+#endif
+  else
+#ifdef DEBUG
+    printf("ERROR: Double LT result is false, expecting true\n");
+#else
+    abort();
+#endif
+
+  a_dble = 0.31;
+  b_dble = 3.10;
+
+  if (__builtin_vec_scalar_cmp_exp_gt(a_dble, b_dble))
+#ifdef DEBUG
+    printf("ERROR: Double GT result is true, expecting false\n");
+#else
+    abort();
+#endif
+  else
+#ifdef DEBUG
+    printf("Double GT result is false, expecting false\n");
+#else
+    ;
+#endif
+
+  a_dble = 3.10;
+  b_dble = 0.31;
+  
+  if (__builtin_vec_scalar_cmp_exp_gt(a_dble, b_dble))
+#ifdef DEBUG
+    printf("Double GT result is true, expecting true\n");
+#else
+    ;
+#endif
+  else
+#ifdef DEBUG
+    printf("ERROR: Double GT result is false, expecting true\n");
+#else
+    abort();
+#endif
+
+  a_dble = NAN;
+  b_dble = NAN;
+  
+  if (__builtin_vec_scalar_cmp_exp_unordered(a_dble, b_dble))
+#ifdef DEBUG
+    printf("Double unordered result is true, expecting true\n");
+#else
+    ;
+#endif
+  else
+#ifdef DEBUG
+    printf("ERROR: Double unordered result is false, expecting true\n");
+#else
+    abort();
+#endif
+
+  a_dble = 3.10;
+  b_dble = 3.10;
+  
+  if (__builtin_vec_scalar_cmp_exp_unordered(a_dble, b_dble))
+#ifdef DEBUG
+    printf("ERROR: Double unordered result is true, expecting false\n");
+#else
+    abort();
+#endif
+  else
+#ifdef DEBUG
+    printf("Double unordered result is false, expecting false\n");
+#else
+    ;
+#endif
+    
+  /* IEEE 128 */
+  a_ieee128 = 3.10;
+  b_ieee128 = 3.10;
+  
+  if (__builtin_vec_scalar_cmp_exp_eq(a_ieee128, b_ieee128))
+#ifdef DEBUG
+    printf("IEEE 128 EQ result is true, expecting true\n");
+#else
+    ;
+#endif
+  else
+#ifdef DEBUG
+    printf("ERROR: IEEE 128 EQ result is false, expecting true\n");
+#else
+    abort();
+#endif
+
+  a_ieee128 = 3.10;
+  b_ieee128 = 31.0;
+  
+  if (__builtin_vec_scalar_cmp_exp_eq(a_ieee128, b_ieee128))
+#ifdef DEBUG
+    printf("ERROR: IEEE 128 EQ result is true, expecting false\n");
+#else
+    abort();
+#endif
+  else
+#ifdef DEBUG
+    printf("IEEE 128 EQ result is false, expecting false\n");
+#else
+    ;
+#endif
+
+  a_ieee128 = 3.10;
+  b_ieee128 = 3.10;
+
+  if (__builtin_vec_scalar_cmp_exp_lt(a_ieee128, b_ieee128))
+#ifdef DEBUG
+    printf("ERROR: IEEE 128 LT result is true, expecting false\n");
+#else
+    abort();
+#endif
+  else
+#ifdef DEBUG
+    printf("IEEE 128 LT result is false, expecting false\n");
+#else
+    ;
+#endif
+
+  a_ieee128 = 0.31;
+  b_ieee128 = 3.10;
+  
+  if (__builtin_vec_scalar_cmp_exp_lt(a_ieee128, b_ieee128))
+#ifdef DEBUG
+    printf("IEEE 128 LT result is true, expecting true\n");
+#else
+    ;
+#endif
+  else
+#ifdef DEBUG
+    printf("ERROR: IEEE 128 LT result is false, expecting true\n");
+#else
+    abort();
+#endif
+
+  a_ieee128 = 0.31;
+  b_ieee128 = 3.10;
+
+  if (__builtin_vec_scalar_cmp_exp_gt(a_ieee128, b_ieee128))
+#ifdef DEBUG
+    printf("ERROR: IEEE 128 GT result is true, expecting false\n");
+#else
+    abort();
+#endif
+  else
+#ifdef DEBUG
+    printf("IEEE 128 GT result is false, expecting false\n");
+#else
+    ;
+#endif
+
+  a_ieee128 = 3.10;
+  b_ieee128 = 0.31;
+  
+  if (__builtin_vec_scalar_cmp_exp_gt(a_ieee128, b_ieee128))
+#ifdef DEBUG
+    printf("IEEE 128 GT result is true, expecting true\n");
+#else
+    ;
+#endif
+  else
+#ifdef DEBUG
+    printf("ERROR: IEEE 128 GT result is false, expecting true\n");
+#else
+    abort();
+#endif
+
+  a_ieee128 = NAN_Q;
+  b_ieee128 = NAN_Q;
+  
+  if (__builtin_vec_scalar_cmp_exp_unordered(a_ieee128, b_ieee128))
+#ifdef DEBUG
+    printf("IEEE unordered result is true, expecting true\n");
+#else
+    ;
+#endif
+  else
+#ifdef DEBUG
+    printf("ERROR: IEEE unordered result is false, expecting true\n");
+#else
+    abort();
+#endif
+
+  a_ieee128 = 3.10;
+  b_ieee128 = 3.10;
+  
+  if (__builtin_vec_scalar_cmp_exp_unordered(a_ieee128, b_ieee128))
+#ifdef DEBUG
+    printf("ERROR: IEEE unordered result is true, expecting false\n");
+#else
+    abort();
+#endif
+  else
+#ifdef DEBUG
+    printf("IEEE unordered result is false, expecting false\n");
+#else
+    ;
+#endif
+}