diff mbox series

[v6,11/18] target/mips: Add emulation of non-MXU MULL within MXU decoding engine

Message ID 1540311509-23970-12-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series target/mips: Add limited support for Ingenic's MXU ASE | expand

Commit Message

Aleksandar Markovic Oct. 23, 2018, 4:18 p.m. UTC 
From: Craig Janeczek <jancraig@amazon.com>

Add emulation of non-MXU MULL within MXU decoding engine.

Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5bcf6a4..29df4ce 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1654,7 +1654,7 @@  enum {
 enum {
     OPC_MXU_S32MADD  = 0x00,
     OPC_MXU_S32MADDU = 0x01,
-    /* not assigned 0x02 */
+    OPC__MXU_MUL     = 0x02,
     OPC_MXU__POOL00  = 0x03,
     OPC_MXU_S32MSUB  = 0x04,
     OPC_MXU_S32MSUBU = 0x05,
@@ -24788,6 +24788,18 @@  static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         MIPS_INVAL("OPC_MXU_S32MADDU");
         generate_exception_end(ctx, EXCP_RI);
         break;
+    case OPC__MXU_MUL:     /* 0x2 - unused in MXU specs */
+        {
+            uint32_t  rs, rt, rd, op1;
+
+            rs = extract32(ctx->opcode, 21, 5);
+            rt = extract32(ctx->opcode, 16, 5);
+            rd = extract32(ctx->opcode, 11, 5);
+            op1 = MASK_SPECIAL2(ctx->opcode);
+
+            gen_arith(ctx, op1, rd, rs, rt);
+        }
+        break;
     case OPC_MXU__POOL00:
         decode_opc_mxu__pool00(env, ctx);
         break;