diff mbox series

[v6,13/18] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch

Message ID 1540311509-23970-14-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series target/mips: Add limited support for Ingenic's MXU ASE | expand

Commit Message

Aleksandar Markovic Oct. 23, 2018, 4:18 p.m. UTC 
From: Aleksandar Markovic <amarkovic@wavecomp.com>

Move MUL, S32M2I, S32I2M handling out of switch. These are all
instructions that do not depend on MXU_EN flag of MXU_CR.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 41 +++++++++++++++++++++++------------------
 1 file changed, 23 insertions(+), 18 deletions(-)
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index c8c71c4..111affb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24859,6 +24859,29 @@  static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
 {
     uint32_t opcode = extract32(ctx->opcode, 0, 6);
 
+    if (opcode == OPC__MXU_MUL) {
+        uint32_t  rs, rt, rd, op1;
+
+        rs = extract32(ctx->opcode, 21, 5);
+        rt = extract32(ctx->opcode, 16, 5);
+        rd = extract32(ctx->opcode, 11, 5);
+        op1 = MASK_SPECIAL2(ctx->opcode);
+
+        gen_arith(ctx, op1, rd, rs, rt);
+
+        return;
+    }
+
+    if (opcode == OPC_MXU_S32M2I) {
+        gen_mxu_s32m2i(ctx);
+        return;
+    }
+
+    if (opcode == OPC_MXU_S32I2M) {
+        gen_mxu_s32i2m(ctx);
+        return;
+    }
+
     switch (opcode) {
     case OPC_MXU_S32MADD:
         /* TODO: Implement emulation of S32MADD instruction. */
@@ -24870,18 +24893,6 @@  static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         MIPS_INVAL("OPC_MXU_S32MADDU");
         generate_exception_end(ctx, EXCP_RI);
         break;
-    case OPC__MXU_MUL:     /* 0x2 - unused in MXU specs */
-        {
-            uint32_t  rs, rt, rd, op1;
-
-            rs = extract32(ctx->opcode, 21, 5);
-            rt = extract32(ctx->opcode, 16, 5);
-            rd = extract32(ctx->opcode, 11, 5);
-            op1 = MASK_SPECIAL2(ctx->opcode);
-
-            gen_arith(ctx, op1, rd, rs, rt);
-        }
-        break;
     case OPC_MXU__POOL00:
         decode_opc_mxu__pool00(env, ctx);
         break;
@@ -25033,12 +25044,6 @@  static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         MIPS_INVAL("OPC_MXU_S16SDI");
         generate_exception_end(ctx, EXCP_RI);
         break;
-    case OPC_MXU_S32M2I:
-        gen_mxu_s32m2i(ctx);
-        break;
-    case OPC_MXU_S32I2M:
-        gen_mxu_s32i2m(ctx);
-        break;
     case OPC_MXU_D32SLL:
         /* TODO: Implement emulation of D32SLL instruction. */
         MIPS_INVAL("OPC_MXU_D32SLL");