Disable interrupts on Cortex M3 (lm3s6965evb)

Message ID BANLkTinsuj1WgejwuZgz9Q6YhTrN1STWnA@mail.gmail.com
State New
Headers show

Commit Message

Peter Maydell June 5, 2011, 1:44 p.m.
On 5 June 2011 14:06, Sebastian Huber
<sebastian.huber@embedded-brains.de> wrote:
> I think the interrupt handling logic for ARMv7M is wrong in cpu-exec.c
> line 470.  Please have a look at the attached patch.

This doesn't look right -- it changes the behaviour in the
case where we aren't an M profile CPU.

In any case, M profile exception priority handling is sufficiently
complicated that any change which only looks at PRIMASK (which is
effectively what the change to look at CPSR_I here is doing) is
almost certainly wrong. I think that whatever is raising the
interrupt should be looking at the CPU priority and not raising it
in the first place.

(It looks suspiciously as if most of the v7M priority handling
is simply missing from QEMU, ie you have bigger problems than
can be fixed by a small patch like this...)

-- PMM


--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -470,8 +470,8 @@  int cpu_exec(CPUState *env1)
                        We avoid this by disabling interrupts when
                        pc contains a magic address.  */
                     if (interrupt_request & CPU_INTERRUPT_HARD
-                        && ((IS_M(env) && env->regs[15] < 0xfffffff0)
-                            || !(env->uncached_cpsr & CPSR_I))) {
+                        && !(env->uncached_cpsr & CPSR_I)
+                        && (IS_M(env) && env->regs[15] < 0xfffffff0)) {
                         env->exception_index = EXCP_IRQ;
                         next_tb = 0;