From patchwork Sun Jun 5 13:06:29 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Disable interrupts on Cortex M3 (lm3s6965evb) Date: Sun, 05 Jun 2011 03:06:29 -0000 From: Sebastian Huber X-Patchwork-Id: 98762 Message-Id: <4DEB7F55.9030700@embedded-brains.de> To: qemu-devel@nongnu.org Cc: Paul Brook On 05/06/11 12:31, Sebastian Huber wrote: > Hello, > > how can I disable interrupts on the Cortex M3 based board LM3S6965EVB? > Even if I set PRIMASK, FAULTMASK and BASEPRI to 1 the SYSTICK interrupt > handler gets called. > > Have a nice day! > I think the interrupt handling logic for ARMv7M is wrong in cpu-exec.c line 470. Please have a look at the attached patch. >From b424c34d0202950307b3a12778a06834917b2947 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Sun, 5 Jun 2011 14:57:17 +0200 Subject: [PATCH] Fixed interrupt handling for ARMv7M. --- cpu-exec.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu-exec.c b/cpu-exec.c index 6ddd8dd..2782076 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -470,8 +470,8 @@ int cpu_exec(CPUState *env1) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->uncached_cpsr & CPSR_I))) { + && !(env->uncached_cpsr & CPSR_I) + && (IS_M(env) && env->regs[15] < 0xfffffff0)) { env->exception_index = EXCP_IRQ; do_interrupt(env); next_tb = 0; -- 1.7.1