diff mbox series

[U-Boot,14/30] riscv: complete the list of exception codes

Message ID	20181019220743.15020-15-lukas.auer@aisec.fraunhofer.de
State	Superseded
Delegated to:	Andes
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Lukas Auer <lukas.auer@aisec.fraunhofer.de> To: <u-boot@lists.denx.de> Date: Sat, 20 Oct 2018 00:07:27 +0200 Message-ID: <20181019220743.15020-15-lukas.auer@aisec.fraunhofer.de> In-Reply-To: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> References: <20181019220743.15020-1-lukas.auer@aisec.fraunhofer.de> MIME-Version: 1.0 Cc: Greentime Hu <green.hu@gmail.com> Subject: [U-Boot] [PATCH 14/30] riscv: complete the list of exception codes Precedence: list Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	General fixes / cleanup for RISC-V and improvements to qemu-riscv \| expand [U-Boot,00/30] General fixes / cleanup for RISC-V and improvements to qemu-riscv [U-Boot,01/30] tools: .gitignore: add prelink-riscv [U-Boot,02/30] riscv: ignore device tree binaries [U-Boot,03/30] dts: riscv: update makefile to also clean the RISC-V dts directory [U-Boot,04/30] riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I [U-Boot,05/30] riscv: select CONFIG_PHYS_64BIT on RV64I systems [U-Boot,06/30] riscv: add Kconfig entries for the C and A ISA extensions [U-Boot,07/30] riscv: set -march and -mabi based on the Kconfig configuration [U-Boot,08/30] riscv: add Kconfig entries for the code model [U-Boot,09/30] riscv: move target selection into separate file [U-Boot,10/30] riscv: enable -fdata-sections [U-Boot,11/30] riscv: fix use of incorrectly sized variables [U-Boot,12/30] riscv: make use of the barrier functions from Linux [U-Boot,13/30] riscv: do not reimplement generic io functions [U-Boot,14/30] riscv: complete the list of exception codes [U-Boot,15/30] riscv: treat undefined exception codes as reserved [U-Boot,16/30] riscv: hang on unhandled exceptions [U-Boot,17/30] riscv: implement the invalidate_icache_* functions [U-Boot,18/30] riscv: invalidate the instruction cache before jumping to Linux [U-Boot,19/30] riscv: fix inconsistent use of spaces and tabs in start.S [U-Boot,20/30] riscv: align mtvec on a 4-byte boundary [U-Boot,21/30] riscv: remove CONFIG_INIT_CRITICAL [U-Boot,22/30] riscv: remove unused labels in start.S [U-Boot,23/30] riscv: do not blindly modify the mstatus CSR [U-Boot,24/30] riscv: save hart ID and device tree passed by prior boot stage [U-Boot,25/30] riscv: qemu: use device tree passed by prior boot stage [U-Boot,26/30] bdinfo: riscv: print fdt_blob address [U-Boot,27/30] riscv: qemu: support booting Linux [U-Boot,28/30] riscv: align bootm implementation with that of other architectures [U-Boot,29/30] dm: core: add missing prototype for ofnode_read_u64 [U-Boot,30/30] riscv: qemu: detect and boot the kernel passed by QEMU

Commit Message

Lukas Auer Oct. 19, 2018, 10:07 p.m. UTC

Only the first four exception codes are defined. Add the missing
exception codes from the definition in RISC-V Privileged Architecture
Version 1.10.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---

 arch/riscv/lib/interrupts.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

Comments

Bin Meng Oct. 22, 2018, 7:36 a.m. UTC | #1

On Sat, Oct 20, 2018 at 6:10 AM Lukas Auer
<lukas.auer@aisec.fraunhofer.de> wrote:
>
> Only the first four exception codes are defined. Add the missing
> exception codes from the definition in RISC-V Privileged Architecture
> Version 1.10.
>
> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> ---
>
>  arch/riscv/lib/interrupts.c | 13 ++++++++++++-
>  1 file changed, 12 insertions(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Rick Chen Oct. 23, 2018, 6:22 a.m. UTC | #2

> > > Only the first four exception codes are defined. Add the missing
> > > exception codes from the definition in RISC-V Privileged Architecture
> > > Version 1.10.
> > >
> > > Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
> > > ---
> > >
> > >  arch/riscv/lib/interrupts.c | 13 ++++++++++++-
> > >  1 file changed, 12 insertions(+), 1 deletion(-)
> > >
> >
> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Reviewed-by: Rick Chen <rick@andestech.com>

diff mbox series

Patch

diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c
index 1c16980a64..3d830c3273 100644
--- a/arch/riscv/lib/interrupts.c
+++ b/arch/riscv/lib/interrupts.c
@@ -67,7 +67,18 @@  static void _exit_trap(ulong code, ulong epc, struct pt_regs *regs)
 		"Instruction access fault",
 		"Illegal instruction",
 		"Breakpoint",
-		"Load address misaligned"
+		"Load address misaligned",
+		"Load access fault",
+		"Store/AMO address misaligned",
+		"Store/AMO access fault",
+		"Environment call from U-mode",
+		"Environment call from S-mode",
+		"Reserved",
+		"Environment call from M-mode",
+		"Instruction page fault",
+		"Load page fault",
+		"Reserved",
+		"Store/AMO page fault",
 	};
 
 	printf("exception code: %ld , %s , epc %016lx , ra %016lx\n",