diff mbox series

[PULL,23/45] target/arm: Don't call tcg_clear_temp_count

Message ID	20181019165735.22511-24-peter.maydell@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Date: Fri, 19 Oct 2018 17:57:13 +0100 Message-Id: <20181019165735.22511-24-peter.maydell@linaro.org> In-Reply-To: <20181019165735.22511-1-peter.maydell@linaro.org> References: <20181019165735.22511-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 23/45] target/arm: Don't call tcg_clear_temp_count Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/45] ssi-sd: Make devices picking up backends unavailable with -device \| expand [PULL,01/45] ssi-sd: Make devices picking up backends unavailable with -device [PULL,02/45] target/arm: Add support for VCPU event states [PULL,03/45] target/arm: Move some system registers into a substructure [PULL,04/45] target/arm: V8M should not imply V7VE [PULL,05/45] target/arm: Convert v8 extensions from feature bits to isar tests [PULL,06/45] target/arm: Convert division from feature bits to isar0 tests [PULL,07/45] target/arm: Convert jazelle from feature bit to isar1 test [PULL,08/45] target/arm: Convert t32ee from feature bit to isar3 test [PULL,09/45] target/arm: Convert sve from feature bit to aa64pfr0 test [PULL,10/45] target/arm: Convert v8.2-fp16 from feature bit to aa64pfr0 test [PULL,11/45] target/arm: Improve debug logging of AArch32 exception return [PULL,12/45] target/arm: Make switch_mode() file-local [PULL,13/45] target/arm: Implement HCR.FB [PULL,14/45] target/arm: Implement HCR.DC [PULL,15/45] target/arm: ISR_EL1 bits track virtual interrupts if IMO/FMO set [PULL,16/45] target/arm: Implement HCR.VI and VF [PULL,17/45] target/arm: Implement HCR.PTW [PULL,18/45] target/arm: New utility function to extract EC from syndrome [PULL,19/45] target/arm: Get IL bit correct for v7 syndrome values [PULL,20/45] target/arm: Report correct syndrome for FP/SIMD traps to Hyp mode [PULL,21/45] hw/arm/boot: Increase compliance with kernel arm64 boot protocol [PULL,22/45] target/arm: Hoist address increment for vector memory ops [PULL,23/45] target/arm: Don't call tcg_clear_temp_count [PULL,24/45] target/arm: Use tcg_gen_gvec_dup_i64 for LD[1-4]R [PULL,25/45] target/arm: Promote consecutive memory ops for aa64 [PULL,26/45] target/arm: Mark some arrays const [PULL,27/45] target/arm: Use gvec for NEON VDUP [PULL,28/45] target/arm: Use gvec for NEON VMOV, VMVN, VBIC & VORR (immediate) [PULL,29/45] target/arm: Use gvec for NEON_3R_LOGIC insns [PULL,30/45] target/arm: Use gvec for NEON_3R_VADD_VSUB insns [PULL,31/45] target/arm: Use gvec for NEON_2RM_VMN, NEON_2RM_VNEG [PULL,32/45] target/arm: Use gvec for NEON_3R_VMUL [PULL,33/45] target/arm: Use gvec for VSHR, VSHL [PULL,34/45] target/arm: Use gvec for VSRA [PULL,35/45] target/arm: Use gvec for VSRI, VSLI [PULL,36/45] target/arm: Use gvec for NEON_3R_VML [PULL,37/45] target/arm: Use gvec for NEON_3R_VTST_VCEQ, NEON_3R_VCGT, NEON_3R_VCGE [PULL,38/45] target/arm: Use gvec for NEON VLD all lanes [PULL,39/45] target/arm: Reorg NEON VLD/VST all elements [PULL,40/45] target/arm: Promote consecutive memory ops for aa32 [PULL,41/45] target/arm: Reorg NEON VLD/VST single element to one lane [PULL,42/45] net: cadence_gem: Announce availability of priority queues [PULL,43/45] net: cadence_gem: Announce 64bit addressing support [PULL,44/45] target/arm: Remove writefn from TTBR0_EL3 [PULL,45/45] target/arm: Only flush tlb if ASID changes

Commit Message

Peter Maydell Oct. 19, 2018, 4:57 p.m. UTC

From: Richard Henderson <richard.henderson@linaro.org>

This is done generically in translator_loop.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20181011205206.3552-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 1 -
 target/arm/translate.c     | 1 -
 2 files changed, 2 deletions(-)

diff mbox series

Patch

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 371909620bb..c3a0e5accd8 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -13899,7 +13899,6 @@  static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
 
 static void aarch64_tr_tb_start(DisasContextBase *db, CPUState *cpu)
 {
-    tcg_clear_temp_count();
 }
 
 static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 1bf339a98b6..7d7a48e5b93 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -12701,7 +12701,6 @@  static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
         tcg_gen_movi_i32(tmp, 0);
         store_cpu_field(tmp, condexec_bits);
     }
-    tcg_clear_temp_count();
 }
 
 static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)