From patchwork Thu Jun 2 06:51:41 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 98563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 17112B6FAE for ; Fri, 3 Jun 2011 22:18:38 +1000 (EST) Received: from localhost ([::1]:59539 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QSTKj-0006LU-V9 for incoming@patchwork.ozlabs.org; Fri, 03 Jun 2011 08:18:34 -0400 Received: from eggs.gnu.org ([140.186.70.92]:48995) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QSSmE-0006Mi-PT for qemu-devel@nongnu.org; Fri, 03 Jun 2011 07:43:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QSSmB-0001E1-UI for qemu-devel@nongnu.org; Fri, 03 Jun 2011 07:42:54 -0400 Received: from cantor.suse.de ([195.135.220.2]:36429 helo=mx1.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QSSmA-0001Cr-L6 for qemu-devel@nongnu.org; Fri, 03 Jun 2011 07:42:50 -0400 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id C8CBE94430; Fri, 3 Jun 2011 13:42:48 +0200 (CEST) From: Alexander Graf To: "qemu-devel@nongnu.org Developers" Date: Thu, 2 Jun 2011 08:51:41 +0200 Message-Id: <1306997503-29304-12-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1306997503-29304-1-git-send-email-agraf@suse.de> References: <1306997503-29304-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 X-Received-From: 195.135.220.2 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 11/13] s390x: free tmp explicitly in every opcode for disas_a5() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org The disas_a5() function provided a TCG tmp variable which was populated by the respective opcode implementations, but freed at the end of the function in generic code. That makes it really hard for code review, so let's move the freeing to the same scope as the actual allocation. Signed-off-by: Alexander Graf --- target-s390x/translate.c | 13 ++++++++++++- 1 files changed, 12 insertions(+), 1 deletions(-) diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 5828b5f..afeb5e6 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -2334,18 +2334,22 @@ static void disas_a5(DisasContext *s, int op, int r1, int i2) case 0x0: /* IIHH R1,I2 [RI] */ tmp = tcg_const_i64(i2); tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 48, 16); + tcg_temp_free_i64(tmp); break; case 0x1: /* IIHL R1,I2 [RI] */ tmp = tcg_const_i64(i2); tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 32, 16); + tcg_temp_free_i64(tmp); break; case 0x2: /* IILH R1,I2 [RI] */ tmp = tcg_const_i64(i2); tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 16, 16); + tcg_temp_free_i64(tmp); break; case 0x3: /* IILL R1,I2 [RI] */ tmp = tcg_const_i64(i2); tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 0, 16); + tcg_temp_free_i64(tmp); break; case 0x4: /* NIHH R1,I2 [RI] */ case 0x8: /* OIHH R1,I2 [RI] */ @@ -2370,6 +2374,7 @@ static void disas_a5(DisasContext *s, int op, int r1, int i2) set_cc_nz_u32(s, tmp32); tcg_temp_free_i64(tmp2); tcg_temp_free_i32(tmp32); + tcg_temp_free_i64(tmp); break; case 0x5: /* NIHL R1,I2 [RI] */ case 0x9: /* OIHL R1,I2 [RI] */ @@ -2395,6 +2400,7 @@ static void disas_a5(DisasContext *s, int op, int r1, int i2) set_cc_nz_u32(s, tmp32); tcg_temp_free_i64(tmp2); tcg_temp_free_i32(tmp32); + tcg_temp_free_i64(tmp); break; case 0x6: /* NILH R1,I2 [RI] */ case 0xa: /* OILH R1,I2 [RI] */ @@ -2420,6 +2426,7 @@ static void disas_a5(DisasContext *s, int op, int r1, int i2) set_cc_nz_u32(s, tmp32); tcg_temp_free_i64(tmp2); tcg_temp_free_i32(tmp32); + tcg_temp_free_i64(tmp); break; case 0x7: /* NILL R1,I2 [RI] */ case 0xb: /* OILL R1,I2 [RI] */ @@ -2443,29 +2450,33 @@ static void disas_a5(DisasContext *s, int op, int r1, int i2) set_cc_nz_u32(s, tmp32); /* signedness should not matter here */ tcg_temp_free_i64(tmp2); tcg_temp_free_i32(tmp32); + tcg_temp_free_i64(tmp); break; case 0xc: /* LLIHH R1,I2 [RI] */ tmp = tcg_const_i64( ((uint64_t)i2) << 48 ); store_reg(r1, tmp); + tcg_temp_free_i64(tmp); break; case 0xd: /* LLIHL R1,I2 [RI] */ tmp = tcg_const_i64( ((uint64_t)i2) << 32 ); store_reg(r1, tmp); + tcg_temp_free_i64(tmp); break; case 0xe: /* LLILH R1,I2 [RI] */ tmp = tcg_const_i64( ((uint64_t)i2) << 16 ); store_reg(r1, tmp); + tcg_temp_free_i64(tmp); break; case 0xf: /* LLILL R1,I2 [RI] */ tmp = tcg_const_i64(i2); store_reg(r1, tmp); + tcg_temp_free_i64(tmp); break; default: LOG_DISAS("illegal a5 operation 0x%x\n", op); gen_illegal_opcode(s, 2); return; } - tcg_temp_free_i64(tmp); } static void disas_a7(DisasContext *s, int op, int r1, int i2)