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[14.202.199.226]) by smtp.gmail.com with ESMTPSA id l71-v6sm20616474pgd.31.2018.10.17.07.46.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 17 Oct 2018 07:46:27 -0700 (PDT) From: Nicholas Piggin To: skiboot@lists.ozlabs.org Date: Thu, 18 Oct 2018 00:46:19 +1000 Message-Id: <20181017144619.12638-1-npiggin@gmail.com> X-Mailer: git-send-email 2.18.0 Subject: [Skiboot] [PATCH] asm/head: move unnecessary code out of head X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" head.S should be for things that must be located in low memory, like boot and interrupt entry. Move some code from there into misc.S that is not called from entry routines. The motivation for this patch is work to run skiboot in virtual memory mode, which does not map head.S code. But even without that motivation, it's still good to keep head.S clean. Signed-off-by: Nicholas Piggin --- asm/head.S | 135 +-------------------------------------------------- asm/misc.S | 138 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 139 insertions(+), 134 deletions(-) diff --git a/asm/head.S b/asm/head.S index 803fbf1a..8b9c0483 100644 --- a/asm/head.S +++ b/asm/head.S @@ -23,13 +23,6 @@ #define EPAPR_MAGIC 0x65504150 -/* Power management instructions */ -#define PPC_INST_NAP .long 0x4c000364 -#define PPC_INST_SLEEP .long 0x4c0003a4 -#define PPC_INST_RVWINKLE .long 0x4c0003e4 - -#define PPC_INST_STOP .long 0x4c0002e4 - #define GET_STACK(stack_reg,pir_reg) \ sldi stack_reg,pir_reg,STACK_SHIFT; \ addis stack_reg,stack_reg,CPU_STACKS_OFFSET@ha; \ @@ -491,133 +484,6 @@ call_relocate: .long 0xa6037b7d; /* mtsrr1 r11 */ \ .long 0x2400004c /* rfid */ -.global enable_machine_check -enable_machine_check: - mflr %r0 - bcl 20,31,$+4 -0: mflr %r3 - addi %r3,%r3,(1f - 0b) - mtspr SPR_HSRR0,%r3 - mfmsr %r3 - ori %r3,%r3,MSR_ME - mtspr SPR_HSRR1,%r3 - hrfid -1: mtlr %r0 - blr - -.global disable_machine_check -disable_machine_check: - mflr %r0 - bcl 20,31,$+4 -0: mflr %r3 - addi %r3,%r3,(1f - 0b) - mtspr SPR_HSRR0,%r3 - mfmsr %r3 - li %r4,MSR_ME - andc %r3,%r3,%r4 - mtspr SPR_HSRR1,%r3 - hrfid -1: mtlr %r0 - blr - -pm_save_regs: - SAVE_GPR(2,%r1) - SAVE_GPR(14,%r1) - SAVE_GPR(15,%r1) - SAVE_GPR(16,%r1) - SAVE_GPR(17,%r1) - SAVE_GPR(18,%r1) - SAVE_GPR(19,%r1) - SAVE_GPR(20,%r1) - SAVE_GPR(21,%r1) - SAVE_GPR(22,%r1) - SAVE_GPR(23,%r1) - SAVE_GPR(24,%r1) - SAVE_GPR(25,%r1) - SAVE_GPR(26,%r1) - SAVE_GPR(27,%r1) - SAVE_GPR(28,%r1) - SAVE_GPR(29,%r1) - SAVE_GPR(30,%r1) - SAVE_GPR(31,%r1) - mfcr %r4 - mfxer %r5 - mfspr %r6,SPR_HSPRG0 - mfspr %r7,SPR_HSPRG1 - stw %r4,STACK_CR(%r1) - stw %r5,STACK_XER(%r1) - std %r6,STACK_GPR0(%r1) - std %r7,STACK_GPR1(%r1) - blr - -.global enter_p8_pm_state -enter_p8_pm_state: - /* Before entering map or rvwinkle, we create a stack frame - * and save our non-volatile registers. - * - * We also save these SPRs: - * - * - HSPRG0 in GPR0 slot - * - HSPRG1 in GPR1 slot - * - * - xxx TODO: HIDs - * - TODO: Mask MSR:ME during the process - * - * On entry, r3 indicates: - * - * 0 = nap - * 1 = rvwinkle - */ - mflr %r0 - std %r0,16(%r1) - stdu %r1,-STACK_FRAMESIZE(%r1) - - bl pm_save_regs - - /* Save stack pointer in struct cpu_thread */ - std %r1,CPUTHREAD_SAVE_R1(%r13) - - /* Winkle or nap ? */ - cmpli %cr0,0,%r3,0 - bne 1f - - /* nap sequence */ - ptesync -0: ld %r0,CPUTHREAD_SAVE_R1(%r13) - cmpd cr0,%r0,%r0 - bne 0b - PPC_INST_NAP - b . - - /* rvwinkle sequence */ -1: ptesync -0: ld %r0,CPUTHREAD_SAVE_R1(%r13) - cmpd cr0,%r0,%r0 - bne 0b - PPC_INST_RVWINKLE - b . - -.global enter_p9_pm_lite_state -enter_p9_pm_lite_state: - mtspr SPR_PSSCR,%r3 - PPC_INST_STOP - blr - -.global enter_p9_pm_state -enter_p9_pm_state: - mflr %r0 - std %r0,16(%r1) - stdu %r1,-STACK_FRAMESIZE(%r1) - - bl pm_save_regs - - /* Save stack pointer in struct cpu_thread */ - std %r1,CPUTHREAD_SAVE_R1(%r13) - - mtspr SPR_PSSCR,%r3 - PPC_INST_STOP - b . - /* This is a little piece of code that is copied down to * 0x100 for handling power management wakeups */ @@ -633,6 +499,7 @@ reset_patch_start: .global reset_patch_end reset_patch_end: +.global reset_wakeup reset_wakeup: /* Get PIR */ mfspr %r31,SPR_PIR diff --git a/asm/misc.S b/asm/misc.S index 381590b9..3db96115 100644 --- a/asm/misc.S +++ b/asm/misc.S @@ -24,6 +24,35 @@ .section ".text","ax" .balign 0x10 +.global enable_machine_check +enable_machine_check: + mflr %r0 + bcl 20,31,$+4 +0: mflr %r3 + addi %r3,%r3,(1f - 0b) + mtspr SPR_HSRR0,%r3 + mfmsr %r3 + ori %r3,%r3,MSR_ME + mtspr SPR_HSRR1,%r3 + hrfid +1: mtlr %r0 + blr + +.global disable_machine_check +disable_machine_check: + mflr %r0 + bcl 20,31,$+4 +0: mflr %r3 + addi %r3,%r3,(1f - 0b) + mtspr SPR_HSRR0,%r3 + mfmsr %r3 + li %r4,MSR_ME + andc %r3,%r3,%r4 + mtspr SPR_HSRR1,%r3 + hrfid +1: mtlr %r0 + blr + /* void set_hid0(unsigned long hid0) */ .global set_hid0 set_hid0: @@ -123,3 +152,112 @@ cleanup_global_tlb: ptesync blr + + +/* Power management instructions */ +#define PPC_INST_NAP .long 0x4c000364 +#define PPC_INST_SLEEP .long 0x4c0003a4 +#define PPC_INST_RVWINKLE .long 0x4c0003e4 + +#define PPC_INST_STOP .long 0x4c0002e4 + +#define SAVE_GPR(reg,sp) std %r##reg,STACK_GPR##reg(sp) +#define REST_GPR(reg,sp) ld %r##reg,STACK_GPR##reg(sp) + +pm_save_regs: + SAVE_GPR(2,%r1) + SAVE_GPR(14,%r1) + SAVE_GPR(15,%r1) + SAVE_GPR(16,%r1) + SAVE_GPR(17,%r1) + SAVE_GPR(18,%r1) + SAVE_GPR(19,%r1) + SAVE_GPR(20,%r1) + SAVE_GPR(21,%r1) + SAVE_GPR(22,%r1) + SAVE_GPR(23,%r1) + SAVE_GPR(24,%r1) + SAVE_GPR(25,%r1) + SAVE_GPR(26,%r1) + SAVE_GPR(27,%r1) + SAVE_GPR(28,%r1) + SAVE_GPR(29,%r1) + SAVE_GPR(30,%r1) + SAVE_GPR(31,%r1) + mfcr %r4 + mfxer %r5 + mfspr %r6,SPR_HSPRG0 + mfspr %r7,SPR_HSPRG1 + stw %r4,STACK_CR(%r1) + stw %r5,STACK_XER(%r1) + std %r6,STACK_GPR0(%r1) + std %r7,STACK_GPR1(%r1) + blr + +.global enter_p8_pm_state +enter_p8_pm_state: + /* Before entering map or rvwinkle, we create a stack frame + * and save our non-volatile registers. + * + * We also save these SPRs: + * + * - HSPRG0 in GPR0 slot + * - HSPRG1 in GPR1 slot + * + * - xxx TODO: HIDs + * - TODO: Mask MSR:ME during the process + * + * On entry, r3 indicates: + * + * 0 = nap + * 1 = rvwinkle + */ + mflr %r0 + std %r0,16(%r1) + stdu %r1,-STACK_FRAMESIZE(%r1) + + bl pm_save_regs + + /* Save stack pointer in struct cpu_thread */ + std %r1,CPUTHREAD_SAVE_R1(%r13) + + /* Winkle or nap ? */ + cmpli %cr0,0,%r3,0 + bne 1f + + /* nap sequence */ + ptesync +0: ld %r0,CPUTHREAD_SAVE_R1(%r13) + cmpd cr0,%r0,%r0 + bne 0b + PPC_INST_NAP + b . + + /* rvwinkle sequence */ +1: ptesync +0: ld %r0,CPUTHREAD_SAVE_R1(%r13) + cmpd cr0,%r0,%r0 + bne 0b + PPC_INST_RVWINKLE + b . + +.global enter_p9_pm_lite_state +enter_p9_pm_lite_state: + mtspr SPR_PSSCR,%r3 + PPC_INST_STOP + blr + +.global enter_p9_pm_state +enter_p9_pm_state: + mflr %r0 + std %r0,16(%r1) + stdu %r1,-STACK_FRAMESIZE(%r1) + + bl pm_save_regs + + /* Save stack pointer in struct cpu_thread */ + std %r1,CPUTHREAD_SAVE_R1(%r13) + + mtspr SPR_PSSCR,%r3 + PPC_INST_STOP + b .