From patchwork Wed Oct 17 06:04:45 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dong Aisheng X-Patchwork-Id: 985112 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-gpio-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nxp.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=nxp.com header.i=@nxp.com header.b="MzFvEbCa"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42ZhV34c0dz9s9J for ; Wed, 17 Oct 2018 17:04:59 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727045AbeJQN67 (ORCPT ); Wed, 17 Oct 2018 09:58:59 -0400 Received: from mail-eopbgr50079.outbound.protection.outlook.com ([40.107.5.79]:3824 "EHLO EUR03-VE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726691AbeJQN66 (ORCPT ); Wed, 17 Oct 2018 09:58:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KYXNJqr+t6foSf+Uuu7QCgT9rr85gnuiADKDhTAkI5o=; b=MzFvEbCaq7Oxd6Z4MclUenMIOMgRq+h8e/tdhH4yxZ3PhK6aXxZNNrV+CMjcEazZtqfe/DeA2O89GNgoWimvR1AINdwzYNYMy6jxFS788zn+uOwee/1NnBklkRVNKO0FkaQ5z/ps5Hyp5ullup4qvOpWW8jmZ5hHP8S31DgcScQ= Received: from AM0PR04MB4211.eurprd04.prod.outlook.com (52.134.126.21) by AM0PR04MB4179.eurprd04.prod.outlook.com (52.134.126.13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1228.26; Wed, 17 Oct 2018 06:04:45 +0000 Received: from AM0PR04MB4211.eurprd04.prod.outlook.com ([fe80::25a0:3167:d718:91c1]) by AM0PR04MB4211.eurprd04.prod.outlook.com ([fe80::25a0:3167:d718:91c1%3]) with mapi id 15.20.1228.032; Wed, 17 Oct 2018 06:04:45 +0000 From: "A.s. Dong" To: "linux-gpio@vger.kernel.org" CC: "linux-arm-kernel@lists.infradead.org" , "linus.walleij@linaro.org" , "shawnguo@kernel.org" , "stefan@agner.ch" , "A.s. Dong" , "dongas86@gmail.com" , dl-linux-imx , "kernel@pengutronix.de" , Fabio Estevam , Fabio Estevam Subject: [PATCH V3 1/2] pinctrl: fsl: add scu based pinctrl support Thread-Topic: [PATCH V3 1/2] pinctrl: fsl: add scu based pinctrl support Thread-Index: AQHUZd9N0y/zNYU8fEaJ/x/MHrZqKg== Date: Wed, 17 Oct 2018 06:04:45 +0000 Message-ID: <1539756011-32559-2-git-send-email-aisheng.dong@nxp.com> References: <1539756011-32559-1-git-send-email-aisheng.dong@nxp.com> In-Reply-To: <1539756011-32559-1-git-send-email-aisheng.dong@nxp.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.7.4 x-clientproxiedby: HK0PR01CA0051.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::15) To AM0PR04MB4211.eurprd04.prod.outlook.com (2603:10a6:208:66::21) authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [119.31.174.66] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM0PR04MB4179; 6:uqvbnsABpozNl7URA4kZlMAnVfk10EiLjv+QgW+TeRmc1OV4ZiUsJVWjurkNNBii/3h9DeB4d1Ht01jRHS9CZcWqriYiKBnI6XDeHlBIf7Qg0McbIvyQWk0KBI5N/mc1zumXU19QDiewtmk5AeLttiel4e1FKuGJeCjy9ZsW+wSGte650D9ySfC7dIbOB5jyrbatuT/cFqs+AhQb8ENV0gk7cXsCrb7SAUfg+9//mXEt4lASyv+Lb8Ssy2T4buWBoTXQaVu7WiblpGwE2ide22AuVWTDtK/G5FQyMvRDyjDa40+PQW4yeJucRwKCFzQgV4JOziwQir1UlIGkqOt8D9vft2+PkeUMFMPDhvHsGlh+gnRoFf+mjJvPBGEMQcAdJnFrtojWb1OTdai7HLJq86nIjw6trhBMaqFVpSOskPMPkxx+ydMRcdqikjyC/hpIS3qoKy3lODn8Yo8bjUhkRA==; 5:x/9gXjc3DM1pJ2ogf1VnS25k2eAEj52dvym+UbgOYGwIaIBEZ17mbxDT0UTMl93YiSgOjTWCBHJEAPcoZWhwGp1dwBwJimBGndiFj+GVCa2nDyVWb7n1E6J5OEw4bQ9ol9WchI1a3lWZELeZD9Z48XftZFWHjCI9hXXRqEhL3xY=; 7:fFJ1TIDqXc+nNmt+LR2SiwoQ5apzoJxMxP30ou6UeWKg/wIivg+XE5LTYZ+Eep4akT8VAEjU2UJUe1TZd0ofDFBmC0T+9/lVSr1J3I9td1RXEnP+tY1YzCPnJ/VKQrxPoKYnsFs84717MS6+x7dMHvWfSvVBvY/V0TvNSOE+jrWleHmTAjxyj3B5B6G75wIfQehCiIXLvKcsMPTlleV1gc0nihN6rwCJYUQ7sRkRzRg9LLI6kLLUwSg2G81EoN/i x-ms-office365-filtering-correlation-id: 5ed53ba8-dd6f-4c85-7264-08d633f66fd7 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989299)(5600074)(711020)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7153060)(7193020); SRVR:AM0PR04MB4179; x-ms-traffictypediagnostic: AM0PR04MB4179: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(85827821059158)(185117386973197); x-ms-exchange-senderadcheck: 1 x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(8211001083)(6040522)(2401047)(5005006)(8121501046)(93006095)(93001095)(10201501046)(3002001)(3231355)(944501410)(52105095)(6055026)(149066)(150057)(6041310)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123564045)(20161123562045)(20161123558120)(20161123560045)(201708071742011)(7699051)(76991092); SRVR:AM0PR04MB4179; BCL:0; PCL:0; RULEID:; SRVR:AM0PR04MB4179; x-forefront-prvs: 08286A0BE2 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(366004)(346002)(136003)(396003)(39860400002)(376002)(199004)(189003)(54534003)(186003)(6486002)(102836004)(26005)(76176011)(99286004)(97736004)(8676002)(2900100001)(14444005)(6512007)(256004)(39060400002)(25786009)(4326008)(53936002)(105586002)(5250100002)(53946003)(2501003)(36756003)(2351001)(66066001)(5640700003)(8936002)(106356001)(6436002)(50226002)(5660300001)(386003)(14454004)(6506007)(478600001)(54906003)(6916009)(81166006)(71190400001)(71200400001)(81156014)(2906002)(3846002)(6116002)(486006)(575784001)(86362001)(11346002)(52116002)(446003)(4744004)(476003)(2616005)(68736007)(305945005)(316002)(7736002)(559001)(579004); DIR:OUT; SFP:1101; SCL:1; SRVR:AM0PR04MB4179; H:AM0PR04MB4211.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; A:1; MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: 1Wx6UZyr6bJSvNM5Cab+7uO1eDYokyM23Byf3sWKt6DAOfCeyD+Qa4VifzUPbvJrmUBzYKaTNjMKkGertP/VB4WHYPjlWAWQVZXG5ehazXlPkvZjPtU0Wdom4wwJQsSNaxolsVL6YROeeIzCc457dgj0t5EoP9cO4j6BEs9OhsdUJ9c0YeMtZUeMYBPpipTjSkJ/De8Pd9JWY24JM776GvNHpWZSvwrS/4SbI+XO2a/qehKP9FzO8AiRkmJdSxCSoTS7MzPK/aLoxlTWdpmeSDRZcl6s15I4DJm0GTxjjE8FsCOg97Hg7DtUkLaIGRL0SCSrpBIZ6CX5Dkkb4m2vH6vItbkE2P08MJGxJkPrZIA= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5ed53ba8-dd6f-4c85-7264-08d633f66fd7 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Oct 2018 06:04:45.7080 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB4179 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Some i.MX SoCs (e.g. MX8QXP and MX8QM) contain a system controller that is responsible for controlling the pad setting of the IPs that are present. Communication between the host processor running an OS and the system controller happens through a SCU protocol. This patch classifies the pad settings into two categories: MMIO and SCU. For the original MMIO method, no functional changes except organize them into a few imx_*_mmio() functions. Besides that, we add the SCU based Pad Mux and Pinconf setting support which are implemented in pinctrl-scu.c. Cc: Linus Walleij Cc: Shawn Guo Cc: Fabio Estevam Cc: Stefan Agner Cc: Pengutronix Kernel Team Signed-off-by: Dong Aisheng --- ChangeLog: v2->v3: * no changes v1->v2: * scu firmware headfile path update * structure name and api usage update * move SCU Pad API implementation into driver --- drivers/pinctrl/freescale/Kconfig | 4 + drivers/pinctrl/freescale/Makefile | 1 + drivers/pinctrl/freescale/pinctrl-imx.c | 425 ++++++++++++++++++++------------ drivers/pinctrl/freescale/pinctrl-imx.h | 67 ++++- drivers/pinctrl/freescale/pinctrl-scu.c | 121 +++++++++ 5 files changed, 448 insertions(+), 170 deletions(-) create mode 100644 drivers/pinctrl/freescale/pinctrl-scu.c diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig index dccf64c..94dcdb5 100644 --- a/drivers/pinctrl/freescale/Kconfig +++ b/drivers/pinctrl/freescale/Kconfig @@ -5,6 +5,10 @@ config PINCTRL_IMX select GENERIC_PINCONF select REGMAP +config PINCTRL_IMX_SCU + bool + select PINCTRL_IMX + config PINCTRL_IMX1_CORE bool select PINMUX diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile index 73175b3..7ac8daf 100644 --- a/drivers/pinctrl/freescale/Makefile +++ b/drivers/pinctrl/freescale/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 # Freescale pin control drivers obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o +obj-$(CONFIG_PINCTRL_IMX_SCU) += pinctrl-scu.o obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o obj-$(CONFIG_PINCTRL_IMX1) += pinctrl-imx1.o obj-$(CONFIG_PINCTRL_IMX21) += pinctrl-imx21.o diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index b04edc2..b704f7c 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -57,9 +57,11 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, struct pinctrl_map **map, unsigned *num_maps) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; const struct group_desc *grp; struct pinctrl_map *new_map; struct device_node *parent; + struct imx_pin *pin; int map_num = 1; int i, j; @@ -74,11 +76,14 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, return -EINVAL; } - for (i = 0; i < grp->num_pins; i++) { - struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; - - if (!(pin->config & IMX_NO_PAD_CTL)) - map_num++; + if (info->flags & IMX_USE_SCU) { + map_num += grp->num_pins; + } else { + for (i = 0; i < grp->num_pins; i++) { + pin = &((struct imx_pin *)(grp->data))[i]; + if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) + map_num++; + } } new_map = kmalloc_array(map_num, sizeof(struct pinctrl_map), @@ -103,16 +108,26 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev, /* create config map */ new_map++; for (i = j = 0; i < grp->num_pins; i++) { - struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; - - if (!(pin->config & IMX_NO_PAD_CTL)) { - new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; - new_map[j].data.configs.group_or_pin = + pin = &((struct imx_pin *)(grp->data))[i]; + new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN; + new_map[j].data.configs.group_or_pin = pin_get_name(pctldev, pin->pin); - new_map[j].data.configs.configs = &pin->config; + + if (info->flags & IMX_USE_SCU) { + /* + * For SCU case, we set mux and conf together + * in one IPC call + */ + new_map[j].data.configs.configs = + (unsigned long *)&pin->conf.scu; + new_map[j].data.configs.num_configs = 2; + } else if (!(pin->conf.mmio.config & IMX_NO_PAD_CTL)) { + new_map[j].data.configs.configs = + &pin->conf.mmio.config; new_map[j].data.configs.num_configs = 1; - j++; } + + j++; } dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", @@ -134,19 +149,96 @@ static const struct pinctrl_ops imx_pctrl_ops = { .pin_dbg_show = imx_pin_dbg_show, .dt_node_to_map = imx_dt_node_to_map, .dt_free_map = imx_dt_free_map, - }; +static int imx_pmx_set_one_pin_mmio(struct imx_pinctrl *ipctl, + struct imx_pin *pin) +{ + const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; + const struct imx_pin_reg *pin_reg; + unsigned int pin_id; + + pin_id = pin->pin; + pin_reg = &ipctl->pin_regs[pin_id]; + + if (pin_reg->mux_reg == -1) { + dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", + info->pins[pin_id].name); + return 0; + } + + if (info->flags & SHARE_MUX_CONF_REG) { + u32 reg; + + reg = readl(ipctl->base + pin_reg->mux_reg); + reg &= ~info->mux_mask; + reg |= (pin_mmio->mux_mode << info->mux_shift); + writel(reg, ipctl->base + pin_reg->mux_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, reg); + } else { + writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); + dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", + pin_reg->mux_reg, pin_mmio->mux_mode); + } + + /* + * If the select input value begins with 0xff, it's a quirky + * select input and the value should be interpreted as below. + * 31 23 15 7 0 + * | 0xff | shift | width | select | + * It's used to work around the problem that the select + * input for some pin is not implemented in the select + * input register but in some general purpose register. + * We encode the select input value, width and shift of + * the bit field into input_val cell of pin function ID + * in device tree, and then decode them here for setting + * up the select input bits in general purpose register. + */ + if (pin_mmio->input_val >> 24 == 0xff) { + u32 val = pin_mmio->input_val; + u8 select = val & 0xff; + u8 width = (val >> 8) & 0xff; + u8 shift = (val >> 16) & 0xff; + u32 mask = ((1 << width) - 1) << shift; + /* + * The input_reg[i] here is actually some IOMUXC general + * purpose register, not regular select input register. + */ + val = readl(ipctl->base + pin_mmio->input_reg); + val &= ~mask; + val |= select << shift; + writel(val, ipctl->base + pin_mmio->input_reg); + } else if (pin_mmio->input_reg) { + /* + * Regular select input register can never be at offset + * 0, and we only print register value for regular case. + */ + if (ipctl->input_sel_base) + writel(pin_mmio->input_val, ipctl->input_sel_base + + pin_mmio->input_reg); + else + writel(pin_mmio->input_val, ipctl->base + + pin_mmio->input_reg); + dev_dbg(ipctl->dev, + "==>select_input: offset 0x%x val 0x%x\n", + pin_mmio->input_reg, pin_mmio->input_val); + } + + return 0; +} + static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, unsigned group) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; - const struct imx_pin_reg *pin_reg; - unsigned int npins, pin_id; - int i; - struct group_desc *grp = NULL; - struct function_desc *func = NULL; + struct function_desc *func; + struct group_desc *grp; + struct imx_pin *pin; + unsigned int npins; + int i, err; /* * Configure the mux mode for each pin in the group for a specific @@ -166,72 +258,16 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, func->name, grp->name); for (i = 0; i < npins; i++) { - struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; - - pin_id = pin->pin; - pin_reg = &ipctl->pin_regs[pin_id]; - - if (pin_reg->mux_reg == -1) { - dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n", - info->pins[pin_id].name); - continue; - } - - if (info->flags & SHARE_MUX_CONF_REG) { - u32 reg; - reg = readl(ipctl->base + pin_reg->mux_reg); - reg &= ~info->mux_mask; - reg |= (pin->mux_mode << info->mux_shift); - writel(reg, ipctl->base + pin_reg->mux_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, reg); - } else { - writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); - dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", - pin_reg->mux_reg, pin->mux_mode); - } - /* - * If the select input value begins with 0xff, it's a quirky - * select input and the value should be interpreted as below. - * 31 23 15 7 0 - * | 0xff | shift | width | select | - * It's used to work around the problem that the select - * input for some pin is not implemented in the select - * input register but in some general purpose register. - * We encode the select input value, width and shift of - * the bit field into input_val cell of pin function ID - * in device tree, and then decode them here for setting - * up the select input bits in general purpose register. + * For IMX_USE_SCU case, we postpone the mux setting + * until config is set as we can set them together + * in one IPC call */ - if (pin->input_val >> 24 == 0xff) { - u32 val = pin->input_val; - u8 select = val & 0xff; - u8 width = (val >> 8) & 0xff; - u8 shift = (val >> 16) & 0xff; - u32 mask = ((1 << width) - 1) << shift; - /* - * The input_reg[i] here is actually some IOMUXC general - * purpose register, not regular select input register. - */ - val = readl(ipctl->base + pin->input_reg); - val &= ~mask; - val |= select << shift; - writel(val, ipctl->base + pin->input_reg); - } else if (pin->input_reg) { - /* - * Regular select input register can never be at offset - * 0, and we only print register value for regular case. - */ - if (ipctl->input_sel_base) - writel(pin->input_val, ipctl->input_sel_base + - pin->input_reg); - else - writel(pin->input_val, ipctl->base + - pin->input_reg); - dev_dbg(ipctl->dev, - "==>select_input: offset 0x%x val 0x%x\n", - pin->input_reg, pin->input_val); + pin = &((struct imx_pin *)(grp->data))[i]; + if (!(info->flags & IMX_USE_SCU)) { + err = imx_pmx_set_one_pin_mmio(ipctl, pin); + if (err) + return err; } } @@ -301,8 +337,8 @@ static u32 imx_pinconf_parse_generic_config(struct device_node *np, return imx_pinconf_decode_generic_config(ipctl, configs, num_configs); } -static int imx_pinconf_get(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *config) +static int imx_pinconf_get_mmio(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *config) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; @@ -322,9 +358,21 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, return 0; } -static int imx_pinconf_set(struct pinctrl_dev *pctldev, - unsigned pin_id, unsigned long *configs, - unsigned num_configs) +static int imx_pinconf_get(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + if (info->flags & IMX_USE_SCU) + return imx_pinconf_get_scu(pctldev, pin_id, config); + else + return imx_pinconf_get_mmio(pctldev, pin_id, config); +} + +static int imx_pinconf_set_mmio(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); const struct imx_pinctrl_soc_info *info = ipctl->info; @@ -359,19 +407,48 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, return 0; } +static int imx_pinconf_set(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + const struct imx_pinctrl_soc_info *info = ipctl->info; + + if (info->flags & IMX_USE_SCU) + return imx_pinconf_set_scu(pctldev, pin_id, + configs, num_configs); + else + return imx_pinconf_set_mmio(pctldev, pin_id, + configs, num_configs); +} + static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned pin_id) { struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); - const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id]; + const struct imx_pinctrl_soc_info *info = ipctl->info; + const struct imx_pin_reg *pin_reg; unsigned long config; + int ret; - if (!pin_reg || pin_reg->conf_reg == -1) { - seq_puts(s, "N/A"); - return; + if (info->flags & IMX_USE_SCU) { + ret = imx_pinconf_get_scu(pctldev, pin_id, &config); + if (ret) { + dev_err(ipctl->dev, "failed to get %s pinconf\n", + pin_get_name(pctldev, pin_id)); + seq_puts(s, "N/A"); + return; + } + } else { + pin_reg = &ipctl->pin_regs[pin_id]; + if (!pin_reg || pin_reg->conf_reg == -1) { + seq_puts(s, "N/A"); + return; + } + + config = readl(ipctl->base + pin_reg->conf_reg); } - config = readl(ipctl->base + pin_reg->conf_reg); seq_printf(s, "0x%lx", config); } @@ -419,9 +496,63 @@ static const struct pinconf_ops imx_pinconf_ops = { * * SHARE_MUX_CONF_REG: * + * IMX_USE_SCU: + * */ #define FSL_PIN_SIZE 24 #define FSL_PIN_SHARE_SIZE 20 +#define FSL_SCU_PIN_SIZE 12 + +static void imx_pinctrl_parse_pin_mmio(struct imx_pinctrl *ipctl, + unsigned int *pin_id, struct imx_pin *pin, + const __be32 **list_p, + struct device_node *np) +{ + const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin_mmio *pin_mmio = &pin->conf.mmio; + struct imx_pin_reg *pin_reg; + const __be32 *list = *list_p; + u32 mux_reg, conf_reg; + u32 config; + + mux_reg = be32_to_cpu(*list++); + + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) + mux_reg = -1; + + if (info->flags & SHARE_MUX_CONF_REG) { + conf_reg = mux_reg; + } else { + conf_reg = be32_to_cpu(*list++); + if (!conf_reg) + conf_reg = -1; + } + + *pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; + pin_reg = &ipctl->pin_regs[*pin_id]; + pin->pin = *pin_id; + pin_reg->mux_reg = mux_reg; + pin_reg->conf_reg = conf_reg; + pin_mmio->input_reg = be32_to_cpu(*list++); + pin_mmio->mux_mode = be32_to_cpu(*list++); + pin_mmio->input_val = be32_to_cpu(*list++); + + if (info->generic_pinconf) { + /* generic pin config decoded */ + pin_mmio->config = imx_pinconf_parse_generic_config(np, ipctl); + } else { + /* legacy pin config read from devicetree */ + config = be32_to_cpu(*list++); + + /* SION bit is in mux register */ + if (config & IMX_PAD_SION) + pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; + pin_mmio->config = config & ~IMX_PAD_SION; + } + + dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[*pin_id].name, + pin_mmio->mux_mode, pin_mmio->config); +} static int imx_pinctrl_parse_groups(struct device_node *np, struct group_desc *grp, @@ -429,14 +560,16 @@ static int imx_pinctrl_parse_groups(struct device_node *np, u32 index) { const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin *pin; int size, pin_size; const __be32 *list; int i; - u32 config; dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name); - if (info->flags & SHARE_MUX_CONF_REG) + if (info->flags & IMX_USE_SCU) + pin_size = FSL_SCU_PIN_SIZE; + else if (info->flags & SHARE_MUX_CONF_REG) pin_size = FSL_PIN_SHARE_SIZE; else pin_size = FSL_PIN_SIZE; @@ -473,9 +606,6 @@ static int imx_pinctrl_parse_groups(struct device_node *np, return -EINVAL; } - /* first try to parse the generic pin config */ - config = imx_pinconf_parse_generic_config(np, ipctl); - grp->num_pins = size / pin_size; grp->data = devm_kcalloc(ipctl->dev, grp->num_pins, sizeof(struct imx_pin), @@ -487,48 +617,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np, return -ENOMEM; for (i = 0; i < grp->num_pins; i++) { - u32 mux_reg = be32_to_cpu(*list++); - u32 conf_reg; - unsigned int pin_id; - struct imx_pin_reg *pin_reg; - struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i]; - - if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) - mux_reg = -1; - - if (info->flags & SHARE_MUX_CONF_REG) { - conf_reg = mux_reg; - } else { - conf_reg = be32_to_cpu(*list++); - if (!conf_reg) - conf_reg = -1; - } - - pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4; - pin_reg = &ipctl->pin_regs[pin_id]; - pin->pin = pin_id; - grp->pins[i] = pin_id; - pin_reg->mux_reg = mux_reg; - pin_reg->conf_reg = conf_reg; - pin->input_reg = be32_to_cpu(*list++); - pin->mux_mode = be32_to_cpu(*list++); - pin->input_val = be32_to_cpu(*list++); - - if (info->generic_pinconf) { - /* generic pin config decoded */ - pin->config = config; - } else { - /* legacy pin config read from devicetree */ - config = be32_to_cpu(*list++); - - /* SION bit is in mux register */ - if (config & IMX_PAD_SION) - pin->mux_mode |= IOMUXC_CONFIG_SION; - pin->config = config & ~IMX_PAD_SION; - } - - dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name, - pin->mux_mode, pin->config); + pin = &((struct imx_pin *)(grp->data))[i]; + if (info->flags & IMX_USE_SCU) + imx_pinctrl_parse_pin_scu(ipctl, &grp->pins[i], + pin, &list); + else + imx_pinctrl_parse_pin_mmio(ipctl, &grp->pins[i], + pin, &list, np); } return 0; @@ -700,35 +795,37 @@ int imx_pinctrl_probe(struct platform_device *pdev, if (!ipctl) return -ENOMEM; - ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, - info->npins, sizeof(*ipctl->pin_regs), - GFP_KERNEL); - if (!ipctl->pin_regs) - return -ENOMEM; + if (!(info->flags & IMX_USE_SCU)) { + ipctl->pin_regs = devm_kmalloc_array(&pdev->dev, info->npins, + sizeof(*ipctl->pin_regs), + GFP_KERNEL); + if (!ipctl->pin_regs) + return -ENOMEM; - for (i = 0; i < info->npins; i++) { - ipctl->pin_regs[i].mux_reg = -1; - ipctl->pin_regs[i].conf_reg = -1; - } + for (i = 0; i < info->npins; i++) { + ipctl->pin_regs[i].mux_reg = -1; + ipctl->pin_regs[i].conf_reg = -1; + } - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ipctl->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(ipctl->base)) - return PTR_ERR(ipctl->base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + ipctl->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(ipctl->base)) + return PTR_ERR(ipctl->base); - if (of_property_read_bool(dev_np, "fsl,input-sel")) { - np = of_parse_phandle(dev_np, "fsl,input-sel", 0); - if (!np) { - dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); - return -EINVAL; - } + if (of_property_read_bool(dev_np, "fsl,input-sel")) { + np = of_parse_phandle(dev_np, "fsl,input-sel", 0); + if (!np) { + dev_err(&pdev->dev, "iomuxc fsl,input-sel property not found\n"); + return -EINVAL; + } - ipctl->input_sel_base = of_iomap(np, 0); - of_node_put(np); - if (!ipctl->input_sel_base) { - dev_err(&pdev->dev, - "iomuxc input select base address not found\n"); - return -ENOMEM; + ipctl->input_sel_base = of_iomap(np, 0); + of_node_put(np); + if (!ipctl->input_sel_base) { + dev_err(&pdev->dev, + "iomuxc input select base address not found\n"); + return -ENOMEM; + } } } diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 4b8225c..98a4889 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -19,16 +19,14 @@ struct platform_device; extern struct pinmux_ops imx_pmx_ops; /** - * struct imx_pin - describes a single i.MX pin - * @pin: the pin_id of this pin + * struct imx_pin_mmio - MMIO pin configurations * @mux_mode: the mux mode for this pin. * @input_reg: the select input register offset for this pin if any * 0 if no select input setting needed. * @input_val: the select input value for this pin. * @configs: the config for this pin. */ -struct imx_pin { - unsigned int pin; +struct imx_pin_mmio { unsigned int mux_mode; u16 input_reg; unsigned int input_val; @@ -36,6 +34,29 @@ struct imx_pin { }; /** + * struct imx_pin_scu - SCU pin configurations + * @mux: the mux mode for this pin. + * @configs: the config for this pin. + */ +struct imx_pin_scu { + unsigned int mux_mode; + unsigned long config; +}; + +/** + * struct imx_pin - describes a single i.MX pin + * @pin: the pin_id of this pin + * @conf: config type of this pin, either mmio or scu + */ +struct imx_pin { + unsigned int pin; + union { + struct imx_pin_mmio mmio; + struct imx_pin_scu scu; + } conf; +}; + +/** * struct imx_pin_reg - describe a pin reg map * @mux_reg: mux register offset * @conf_reg: config register offset @@ -99,8 +120,9 @@ struct imx_pinctrl { #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ { .param = p, .mask = m, .shift = o, .invert = true, } -#define SHARE_MUX_CONF_REG 0x1 -#define ZERO_OFFSET_VALID 0x2 +#define SHARE_MUX_CONF_REG BIT(0) +#define ZERO_OFFSET_VALID BIT(1) +#define IMX_USE_SCU BIT(2) #define NO_MUX 0x0 #define NO_PAD 0x0 @@ -113,4 +135,37 @@ struct imx_pinctrl { int imx_pinctrl_probe(struct platform_device *pdev, const struct imx_pinctrl_soc_info *info); + +#ifdef CONFIG_PINCTRL_IMX_SCU +#define BM_PAD_CTL_GP_ENABLE BIT(30) +#define BM_PAD_CTL_IFMUX_ENABLE BIT(31) +#define BP_PAD_CTL_IFMUX 27 + +int imx_pinctrl_sc_ipc_init(struct platform_device *pdev); +int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *config); +int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *configs, unsigned num_configs); +void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, + unsigned int *pin_id, struct imx_pin *pin, + const __be32 **list_p); +#else +static inline int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *config) +{ + return -EINVAL; +} +static inline int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, + unsigned pin_id, unsigned long *configs, + unsigned num_configs) +{ + return -EINVAL; +} +static inline void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, + unsigned int *pin_id, + struct imx_pin *pin, + const __be32 **list_p) +{ +} +#endif #endif /* __DRIVERS_PINCTRL_IMX_H */ diff --git a/drivers/pinctrl/freescale/pinctrl-scu.c b/drivers/pinctrl/freescale/pinctrl-scu.c new file mode 100644 index 0000000..b3e5f4a --- /dev/null +++ b/drivers/pinctrl/freescale/pinctrl-scu.c @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017~2018 NXP + * Dong Aisheng + */ + +#include +#include +#include +#include +#include + +#include "../core.h" +#include "pinctrl-imx.h" + +enum pad_func_e { + IMX_SC_PAD_FUNC_SET = 15, + IMX_SC_PAD_FUNC_GET = 16, +}; + +struct imx_sc_msg_req_pad_set { + struct imx_sc_rpc_msg hdr; + u32 val; + u16 pad; +} __packed; + +struct imx_sc_msg_req_pad_get { + struct imx_sc_rpc_msg hdr; + u16 pad; +} __packed; + +struct imx_sc_msg_resp_pad_get { + struct imx_sc_rpc_msg hdr; + u32 val; +} __packed; + +struct imx_sc_ipc *pinctrl_ipc_handle; + +int imx_pinctrl_sc_ipc_init(struct platform_device *pdev) +{ + return imx_scu_get_handle(&pinctrl_ipc_handle); +} + +int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *config) +{ + struct imx_sc_msg_req_pad_get msg; + struct imx_sc_msg_resp_pad_get *resp; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_PAD; + hdr->func = (uint8_t)IMX_SC_PAD_FUNC_GET; + hdr->size = 2; + + msg.pad = pin_id; + + ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true); + if (ret) + return ret; + + resp = (struct imx_sc_msg_resp_pad_get *)&msg; + *config = resp->val; + + return 0; +} + +int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, + unsigned long *configs, unsigned num_configs) +{ + struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev); + struct imx_sc_msg_req_pad_set msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + unsigned int mux = configs[0]; + unsigned int conf = configs[1]; + unsigned int val; + int ret; + + /* + * Set mux and conf together in one IPC call + */ + WARN_ON(num_configs != 2); + + val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE; + val |= mux << BP_PAD_CTL_IFMUX; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = (uint8_t)IMX_SC_RPC_SVC_PAD; + hdr->func = (uint8_t)IMX_SC_PAD_FUNC_SET; + hdr->size = 3; + + msg.pad = pin_id; + msg.val = val; + + ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true); + + dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n", + pin_id, conf, val); + + return ret; +} + +void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, + unsigned int *pin_id, struct imx_pin *pin, + const __be32 **list_p) +{ + const struct imx_pinctrl_soc_info *info = ipctl->info; + struct imx_pin_scu *pin_scu = &pin->conf.scu; + const __be32 *list = *list_p; + + pin->pin = be32_to_cpu(*list++); + *pin_id = pin->pin; + pin_scu->mux_mode = be32_to_cpu(*list++); + pin_scu->config = be32_to_cpu(*list++); + *list_p = list; + + dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name, + pin_scu->mux_mode, pin_scu->config); +}