Patchwork [committed] Fix PR target/49163

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Submitter Kaz Kojima
Date June 2, 2011, 10:28 p.m.
Message ID <20110603.072816.493590850.kkojima@rr.iij4u.or.jp>
Download mbox | patch
Permalink /patch/98493/
State New
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Comments

Kaz Kojima - June 2, 2011, 10:28 p.m.
Hi,

The attached patch is to fix PR target/49163.
The problem occurs with the unrecognizable insn like

(insn 66 141 110 4 (set (reg:SI 4 r4)
        (sign_extend:SI (subreg:QI (mem/s/v/u/c:DI (plus:SI (reg/f:SI 7 r7 [192])
                        (const_int 12 [0xc])) [3 s2array[1][0].f0+0 S8 A32]) 0))) iii.c:39 164 {*extendqisi2_compact}
     (expr_list:REG_DEAD (reg/f:SI 7 r7 [192])
        (nil)))

which is an intermediate insn in reload.
SH makes the memory address like (plus (reg) (const_int)) invalid
for HI/QImode because SH's mov.b instruction can take only R0 as
the other operand for that memory and compiler can't handle such
case well.  The patch makes constraints for some move insns more
rigid about invalid addresses of this type so to avoid generating
a problematic move insn.
The patch is tested on sh4-unknown-linux-gnu with no new failures.
and the new test is tested also on i686-pc-linux-gnu.
Applied on trunk.

Regards,
	kaz
--
2011-06-02  Kaz Kojima  <kkojima@gcc.gnu.org>

	PR target/49163
	* config/sh/predicates.md (general_movsrc_operand): Return 0
	for memory and memory subreg of which address is an invalid
	indexed address for QI and HImode.
	(general_movdst_operand): Likewise.

[testsuite]
	PR target/49163
	* gcc.c-torture/compile/pr49163.c: New.

Patch

diff -uprN ORIG/trunk/gcc/config/sh/predicates.md trunk/gcc/config/sh/predicates.md
--- ORIG/trunk/gcc/config/sh/predicates.md	2010-04-12 09:52:36.000000000 +0900
+++ trunk/gcc/config/sh/predicates.md	2011-06-02 10:17:40.000000000 +0900
@@ -394,6 +394,18 @@ 
 	return 0;
     }
 
+  if ((mode == QImode || mode == HImode)
+      && (MEM_P (op)
+	  || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
+    {
+      rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
+
+      if (GET_CODE (x) == PLUS
+	  && REG_P (XEXP (x, 0))
+	  && CONST_INT_P (XEXP (x, 1)))
+	return sh_legitimate_index_p (mode, XEXP (x, 1));
+    }
+
   if (TARGET_SHMEDIA
       && (GET_CODE (op) == PARALLEL || GET_CODE (op) == CONST_VECTOR)
       && sh_rep_vec (op, mode))
@@ -419,6 +431,18 @@ 
       && ! (high_life_started || reload_completed))
     return 0;
 
+  if ((mode == QImode || mode == HImode)
+      && (MEM_P (op)
+	  || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
+    {
+      rtx x = XEXP ((MEM_P (op) ? op : SUBREG_REG (op)), 0);
+
+      if (GET_CODE (x) == PLUS
+	  && REG_P (XEXP (x, 0))
+	  && CONST_INT_P (XEXP (x, 1)))
+	return sh_legitimate_index_p (mode, XEXP (x, 1));
+    }
+
   return general_operand (op, mode);
 })
 
diff -uprN ORIG/trunk/gcc/testsuite/gcc.c-torture/compile/pr49163.c trunk/gcc/testsuite/gcc.c-torture/compile/pr49163.c
--- ORIG/trunk/gcc/testsuite/gcc.c-torture/compile/pr49163.c	1970-01-01 09:00:00.000000000 +0900
+++ trunk/gcc/testsuite/gcc.c-torture/compile/pr49163.c	2011-06-02 20:58:31.000000000 +0900
@@ -0,0 +1,35 @@ 
+/* PR target/49163 */
+struct S1
+{
+ unsigned f0:18;
+ int f1;
+} __attribute__ ((packed));
+
+struct S2
+{
+  volatile long long f0;
+  int f1;
+};
+
+struct S1 s1;
+struct S2 s2;
+const struct S2 s2array[2][1] = { };
+
+struct S2 **sptr;
+
+extern int bar (char a, long long b, int * c, long long d, long long e);
+extern int baz (void);
+
+int i;
+int *ptr;
+
+void
+foo (int *arg)
+{
+  for (i = 0; i < 1; i = baz())
+    {
+      *arg = *(int *)sptr;
+      *ptr = bar (*arg, s2.f1, ptr,
+		  bar (s2array[1][0].f0, *arg, ptr, s1.f1, *ptr), *arg);
+    }
+}