| Message ID | 20181015094233.1324-2-aik@ozlabs.ru (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | vfio/spapr_tce: Reworks for NVIDIA V100 + P9 passthrough (part 3) | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | next/apply_patch Successfully applied |
| snowpatch_ozlabs/checkpatch | success | Test checkpatch on branch next |
On Mon, Oct 15, 2018 at 08:42:31PM +1100, Alexey Kardashevskiy wrote: 65;5402;1c> So far we only allowed mapping of MMIO BARs to the userspace. However > there there are GPUs with on-board coherent RAM accessible via side > channels which we also want to map to the userspace. The first client > for this is NVIDIA V100 GPU with NVLink2 direct links to a POWER9 > NPU-enabled CPU; such GPUs have 16GB RAM which is coherently mapped > to the system address space, we are going to export these as an extra > PCI region. > > We already support extra PCI regions and this adds support for mapping > them to the userspace. > > Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > Changes: > v2: > * reverted one of mistakenly removed error checks > --- > drivers/vfio/pci/vfio_pci_private.h | 3 +++ > drivers/vfio/pci/vfio_pci.c | 8 ++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/vfio/pci/vfio_pci_private.h b/drivers/vfio/pci/vfio_pci_private.h > index cde3b5d..86aab05 100644 > --- a/drivers/vfio/pci/vfio_pci_private.h > +++ b/drivers/vfio/pci/vfio_pci_private.h > @@ -59,6 +59,9 @@ struct vfio_pci_regops { > size_t count, loff_t *ppos, bool iswrite); > void (*release)(struct vfio_pci_device *vdev, > struct vfio_pci_region *region); > + int (*mmap)(struct vfio_pci_device *vdev, > + struct vfio_pci_region *region, > + struct vm_area_struct *vma); > }; > > struct vfio_pci_region { > diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c > index d9af440..7923314 100644 > --- a/drivers/vfio/pci/vfio_pci.c > +++ b/drivers/vfio/pci/vfio_pci.c > @@ -1126,6 +1126,14 @@ static int vfio_pci_mmap(void *device_data, struct vm_area_struct *vma) > return -EINVAL; > if ((vma->vm_flags & VM_SHARED) == 0) > return -EINVAL; > + if (index >= VFIO_PCI_NUM_REGIONS) { > + int regnum = index - VFIO_PCI_NUM_REGIONS; > + struct vfio_pci_region *region = vdev->region + regnum; > + > + if (region && region->ops && region->ops->mmap) > + return region->ops->mmap(vdev, region, vma); > + return -EINVAL; > + } > if (index >= VFIO_PCI_ROM_REGION_INDEX) > return -EINVAL; > if (!vdev->bar_mmap_supported[index])
diff --git a/drivers/vfio/pci/vfio_pci_private.h b/drivers/vfio/pci/vfio_pci_private.h index cde3b5d..86aab05 100644 --- a/drivers/vfio/pci/vfio_pci_private.h +++ b/drivers/vfio/pci/vfio_pci_private.h @@ -59,6 +59,9 @@ struct vfio_pci_regops { size_t count, loff_t *ppos, bool iswrite); void (*release)(struct vfio_pci_device *vdev, struct vfio_pci_region *region); + int (*mmap)(struct vfio_pci_device *vdev, + struct vfio_pci_region *region, + struct vm_area_struct *vma); }; struct vfio_pci_region { diff --git a/drivers/vfio/pci/vfio_pci.c b/drivers/vfio/pci/vfio_pci.c index d9af440..7923314 100644 --- a/drivers/vfio/pci/vfio_pci.c +++ b/drivers/vfio/pci/vfio_pci.c @@ -1126,6 +1126,14 @@ static int vfio_pci_mmap(void *device_data, struct vm_area_struct *vma) return -EINVAL; if ((vma->vm_flags & VM_SHARED) == 0) return -EINVAL; + if (index >= VFIO_PCI_NUM_REGIONS) { + int regnum = index - VFIO_PCI_NUM_REGIONS; + struct vfio_pci_region *region = vdev->region + regnum; + + if (region && region->ops && region->ops->mmap) + return region->ops->mmap(vdev, region, vma); + return -EINVAL; + } if (index >= VFIO_PCI_ROM_REGION_INDEX) return -EINVAL; if (!vdev->bar_mmap_supported[index])
So far we only allowed mapping of MMIO BARs to the userspace. However there there are GPUs with on-board coherent RAM accessible via side channels which we also want to map to the userspace. The first client for this is NVIDIA V100 GPU with NVLink2 direct links to a POWER9 NPU-enabled CPU; such GPUs have 16GB RAM which is coherently mapped to the system address space, we are going to export these as an extra PCI region. We already support extra PCI regions and this adds support for mapping them to the userspace. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> --- Changes: v2: * reverted one of mistakenly removed error checks --- drivers/vfio/pci/vfio_pci_private.h | 3 +++ drivers/vfio/pci/vfio_pci.c | 8 ++++++++ 2 files changed, 11 insertions(+)