@@ -620,7 +620,10 @@ const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) | (1 << CP0C3_MSAP),
+ .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
+ .CP0_Config4_rw_bitmask = 0,
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn),
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0,
.SYNCI_Step = 32,
@@ -634,7 +637,7 @@ const mips_def_t mips_defs[] =
.CP1_fcr31_rw_bitmask = 0xFF83FFFF,
.SEGBITS = 42,
.PABITS = 36,
- .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
+ .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D | ASE_MSA,
.mmu_type = MMU_TYPE_R4000,
},
{