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[v5,21/28] target/mips: Add opcodes for nanoMIPS EVA instructions

Message ID 1539362376-12010-22-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series Misc MIPS fixes and improvements for October 2018 | expand

Commit Message

Aleksandar Markovic Oct. 12, 2018, 4:39 p.m. UTC 
From: Dimitrije Nikolic <dnikolic@wavecomp.com>

Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.

Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/translate.c | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

Comments

Aleksandar Markovic Oct. 12, 2018, 6:40 p.m. UTC | #1 
> Subject: [PATCH v5 21/28] target/mips: Add opcodes for nanoMIPS EVA instructions
>
> From: Dimitrije Nikolic <dnikolic@wavecomp.com>
>
> Add opcodes for nanoMIPS EVA instructions: CACHEE, LBE, LBUE, LHE,
LHUE, LLE, LLWPE, LWE, PREFE, SBE, SCE, SCWPE, SHE, SWE.
>
> Signed-off-by: Dimitrije Nikolic <dnikolic@wavecomp.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
diff mbox series

Patch

diff --git a/target/mips/translate.c b/target/mips/translate.c
index f76dfda..e7bc3d4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -16686,6 +16686,40 @@  enum {
     NM_P_SC      = 0x0b,
 };
 
+/* P.LS.E0 instruction pool */
+enum {
+    NM_LBE      = 0x00,
+    NM_SBE      = 0x01,
+    NM_LBUE     = 0x02,
+    NM_P_PREFE  = 0x03,
+    NM_LHE      = 0x04,
+    NM_SHE      = 0x05,
+    NM_LHUE     = 0x06,
+    NM_CACHEE   = 0x07,
+    NM_LWE      = 0x08,
+    NM_SWE      = 0x09,
+    NM_P_LLE    = 0x0a,
+    NM_P_SCE    = 0x0b,
+};
+
+/* P.PREFE instruction pool */
+enum {
+    NM_SYNCIE   = 0x00,
+    NM_PREFE    = 0x01,
+};
+
+/* P.LLE instruction pool */
+enum {
+    NM_LLE      = 0x00,
+    NM_LLWPE    = 0x01,
+};
+
+/* P.SCE instruction pool */
+enum {
+    NM_SCE      = 0x00,
+    NM_SCWPE    = 0x01,
+};
+
 /* P.LS.WM instruction pool */
 enum {
     NM_LWM       = 0x00,