From patchwork Fri Oct 12 08:48:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Boris Brezillon X-Patchwork-Id: 982919 X-Patchwork-Delegate: tudor.ambarus@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=bootlin.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="lHYK1ZVb"; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42WhWd0KqLz9s3T for ; Fri, 12 Oct 2018 19:55:57 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=ZREYmF61EX/i4E85k5gC9sjFsbwVJFCbBDrD0LF/qds=; b=lHYK1ZVbPfYrriLsl7zpourCW4 uqRXDyfOjvJ3Xw0BBg1t/MpGWni3lqmpi4Ojncy7a/zQ1ELOLkEY3j6mU5HyQUk3YyY0St43sYz06 fGbE7PXzVlqfIEpC33dTmwjoUkpt9QRAox7fW+ykn/pXqgqcMNnJN3wbmH6d/VMCxxec+E/z5FIkk xxGve0Ijsc5CW/3xDWsva6Z+wdd8q199glGnG3fqsB+2BPE75T1EABOexDJaKbiW7wYBGVPnjL80q 9jCXcKUzTyOIdsHpK9wk+HCYKjHAOLYtEsi/iWGOQ3jiE6rA7IC2j54lQxMJLsNx0che6qUgtM0md WrKzF1bA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gAtES-0007P9-F6; Fri, 12 Oct 2018 08:55:40 +0000 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1gAt82-0001mG-VX for linux-mtd@lists.infradead.org; Fri, 12 Oct 2018 08:49:47 +0000 Received: by mail.bootlin.com (Postfix, from userid 110) id 3E99320DBD; Fri, 12 Oct 2018 10:48:58 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.bootlin.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost.localdomain (AAubervilliers-681-1-7-245.w90-88.abo.wanadoo.fr [90.88.129.245]) by mail.bootlin.com (Postfix) with ESMTPSA id 12FF920DDC; Fri, 12 Oct 2018 10:48:32 +0200 (CEST) From: Boris Brezillon To: David Woodhouse , Brian Norris , Boris Brezillon , Marek Vasut , Richard Weinberger , linux-mtd@lists.infradead.org, Yogesh Gaur , Vignesh R , Cyrille Pitchen Subject: [PATCH RFC 14/18] mtd: spi-nor: Clarify where DTR mode applies Date: Fri, 12 Oct 2018 10:48:21 +0200 Message-Id: <20181012084825.23697-15-boris.brezillon@bootlin.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20181012084825.23697-1-boris.brezillon@bootlin.com> References: <20181012084825.23697-1-boris.brezillon@bootlin.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20181012_014903_351286_3021DAD3 X-CRM114-Status: GOOD ( 16.51 ) X-Spam-Score: 0.8 (/) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (0.8 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record 0.8 UPPERCASE_50_75 message body is 50-75% uppercase X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julien Su , Mark Brown , Mason Yang , linux-spi@vger.kernel.org, zhengxunli@mxic.com.tw MIME-Version: 1.0 Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org In its current state, '_DTR' means 'send everything except the instruction in DTR mode'. Clarify that by renaming the macros into _1_xD_xD so that we can later support full DTR modes (where the instruction byte is also sent in DTR mode). Signed-off-by: Boris Brezillon --- drivers/mtd/spi-nor/spi-nor.c | 22 ++++++++-------- include/linux/mtd/spi-nor.h | 61 ++++++++++++++++++++++++++----------------- 2 files changed, 48 insertions(+), 35 deletions(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 9cd8677b8cb2..98dab7f6938e 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -58,25 +58,25 @@ struct spi_nor_pp_command { enum spi_nor_read_command_index { SNOR_CMD_READ, SNOR_CMD_READ_FAST, - SNOR_CMD_READ_1_1_1_DTR, + SNOR_CMD_READ_1_1D_1D, /* Dual SPI */ SNOR_CMD_READ_1_1_2, SNOR_CMD_READ_1_2_2, SNOR_CMD_READ_2_2_2, - SNOR_CMD_READ_1_2_2_DTR, + SNOR_CMD_READ_1_2D_2D, /* Quad SPI */ SNOR_CMD_READ_1_1_4, SNOR_CMD_READ_1_4_4, SNOR_CMD_READ_4_4_4, - SNOR_CMD_READ_1_4_4_DTR, + SNOR_CMD_READ_1_4D_4D, /* Octo SPI */ SNOR_CMD_READ_1_1_8, SNOR_CMD_READ_1_8_8, SNOR_CMD_READ_8_8_8, - SNOR_CMD_READ_1_8_8_DTR, + SNOR_CMD_READ_1_8D_8D, SNOR_CMD_READ_MAX }; @@ -613,9 +613,9 @@ static u8 spi_nor_convert_3to4_read(u8 opcode) { SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B }, { SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B }, - { SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B }, - { SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B }, - { SPINOR_OP_READ_1_4_4_DTR, SPINOR_OP_READ_1_4_4_DTR_4B }, + { SPINOR_OP_READ_1_1D_1D, SPINOR_OP_READ_1_1D_1D_4B }, + { SPINOR_OP_READ_1_2D_2D, SPINOR_OP_READ_1_2D_2D_4B }, + { SPINOR_OP_READ_1_4D_4D, SPINOR_OP_READ_1_4D_4D_4B }, }; return spi_nor_convert_opcode(opcode, spi_nor_3to4_read, @@ -2999,19 +2999,19 @@ static int spi_nor_hwcaps_read2cmd(u32 hwcaps) static const int hwcaps_read2cmd[][2] = { { SNOR_HWCAPS_READ, SNOR_CMD_READ }, { SNOR_HWCAPS_READ_FAST, SNOR_CMD_READ_FAST }, - { SNOR_HWCAPS_READ_1_1_1_DTR, SNOR_CMD_READ_1_1_1_DTR }, + { SNOR_HWCAPS_READ_1_1D_1D, SNOR_CMD_READ_1_1D_1D }, { SNOR_HWCAPS_READ_1_1_2, SNOR_CMD_READ_1_1_2 }, { SNOR_HWCAPS_READ_1_2_2, SNOR_CMD_READ_1_2_2 }, { SNOR_HWCAPS_DPI, SNOR_CMD_READ_2_2_2 }, - { SNOR_HWCAPS_READ_1_2_2_DTR, SNOR_CMD_READ_1_2_2_DTR }, + { SNOR_HWCAPS_READ_1_2D_2D, SNOR_CMD_READ_1_2D_2D }, { SNOR_HWCAPS_READ_1_1_4, SNOR_CMD_READ_1_1_4 }, { SNOR_HWCAPS_READ_1_4_4, SNOR_CMD_READ_1_4_4 }, { SNOR_HWCAPS_QPI, SNOR_CMD_READ_4_4_4 }, - { SNOR_HWCAPS_READ_1_4_4_DTR, SNOR_CMD_READ_1_4_4_DTR }, + { SNOR_HWCAPS_READ_1_4D_4D, SNOR_CMD_READ_1_4D_4D }, { SNOR_HWCAPS_READ_1_1_8, SNOR_CMD_READ_1_1_8 }, { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, { SNOR_HWCAPS_OPI, SNOR_CMD_READ_8_8_8 }, - { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, + { SNOR_HWCAPS_READ_1_8D_8D, SNOR_CMD_READ_1_8D_8D }, }; return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd, diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e497f3b93a74..1035706bc6db 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -81,13 +81,13 @@ #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */ /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */ -#define SPINOR_OP_READ_1_1_1_DTR 0x0d -#define SPINOR_OP_READ_1_2_2_DTR 0xbd -#define SPINOR_OP_READ_1_4_4_DTR 0xed +#define SPINOR_OP_READ_1_1D_1D 0x0d +#define SPINOR_OP_READ_1_2D_2D 0xbd +#define SPINOR_OP_READ_1_4D_4D 0xed -#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e -#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe -#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee +#define SPINOR_OP_READ_1_1D_1D_4B 0x0e +#define SPINOR_OP_READ_1_2D_2D_4B 0xbe +#define SPINOR_OP_READ_1_4D_4D_4B 0xee /* Used for SST flashes only. */ #define SPINOR_OP_BP 0x02 /* Byte program */ @@ -174,7 +174,10 @@ ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \ SNOR_PROTO_DATA_MASK) -#define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */ +/* Double Transfer Rate flags */ +#define SNOR_PROTO_INST_IS_DTR BIT(26) +#define SNOR_PROTO_ADDR_IS_DTR BIT(25) +#define SNOR_PROTO_DATA_IS_DTR BIT(24) #define SNOR_PROTO_INST_2BYTE BIT(31) @@ -182,9 +185,9 @@ (SNOR_PROTO_INST(_inst_nbits) | \ SNOR_PROTO_ADDR(_addr_nbits) | \ SNOR_PROTO_DATA(_data_nbits)) -#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \ - (SNOR_PROTO_IS_DTR | \ - SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)) +#define SNOR_PROTO_1_XD_XD(_nbits) \ + (SNOR_PROTO_DATA_IS_DTR | SNOR_PROTO_ADDR_IS_DTR | \ + SNOR_PROTO_STR(1, _nbits, _nbits)) enum spi_nor_protocol { SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1), @@ -198,15 +201,25 @@ enum spi_nor_protocol { SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4), SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8), - SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1), - SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2), - SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4), - SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8), + SNOR_PROTO_1_1D_1D = SNOR_PROTO_1_XD_XD(1), + SNOR_PROTO_1_2D_2D = SNOR_PROTO_1_XD_XD(2), + SNOR_PROTO_1_4D_4D = SNOR_PROTO_1_XD_XD(4), + SNOR_PROTO_1_8D_8D = SNOR_PROTO_1_XD_XD(8), }; -static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto) +static inline bool spi_nor_protocol_inst_is_dtr(enum spi_nor_protocol proto) { - return !!(proto & SNOR_PROTO_IS_DTR); + return !!(proto & SNOR_PROTO_INST_IS_DTR); +} + +static inline bool spi_nor_protocol_addr_is_dtr(enum spi_nor_protocol proto) +{ + return !!(proto & SNOR_PROTO_ADDR_IS_DTR); +} + +static inline bool spi_nor_protocol_data_is_dtr(enum spi_nor_protocol proto) +{ + return !!(proto & SNOR_PROTO_DATA_IS_DTR); } static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto) @@ -499,22 +512,22 @@ struct spi_nor_hwcaps { #define SNOR_HWCAPS_READ_MASK GENMASK(11, 0) #define SNOR_HWCAPS_READ BIT(0) #define SNOR_HWCAPS_READ_FAST BIT(1) -#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2) +#define SNOR_HWCAPS_READ_1_1D_1D BIT(2) #define SNOR_HWCAPS_READ_DUAL GENMASK(5, 3) #define SNOR_HWCAPS_READ_1_1_2 BIT(3) #define SNOR_HWCAPS_READ_1_2_2 BIT(4) -#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(5) +#define SNOR_HWCAPS_READ_1_2D_2D BIT(5) #define SNOR_HWCAPS_READ_QUAD GENMASK(8, 6) #define SNOR_HWCAPS_READ_1_1_4 BIT(6) #define SNOR_HWCAPS_READ_1_4_4 BIT(7) -#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(8) +#define SNOR_HWCAPS_READ_1_4D_4D BIT(8) #define SNOR_HWCPAS_READ_OCTO GENMASK(11, 9) #define SNOR_HWCAPS_READ_1_1_8 BIT(9) #define SNOR_HWCAPS_READ_1_8_8 BIT(10) -#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(11) +#define SNOR_HWCAPS_READ_1_8D_8D BIT(11) /* * Page Program capabilities. @@ -553,10 +566,10 @@ struct spi_nor_hwcaps { SNOR_HWCAPS_QPI | \ SNOR_HWCAPS_OPI) -#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \ - SNOR_HWCAPS_READ_1_2_2_DTR | \ - SNOR_HWCAPS_READ_1_4_4_DTR | \ - SNOR_HWCAPS_READ_1_8_8_DTR) +#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1D_1D | \ + SNOR_HWCAPS_READ_1_2D_2D | \ + SNOR_HWCAPS_READ_1_4D_4D | \ + SNOR_HWCAPS_READ_1_8D_8D) #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \ SNOR_HWCAPS_PP_MASK | \