diff mbox series

[v4,10/22] target/mips: Add CPO MemoryMapID register

Message ID 1539256947-22807-11-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series Misc MIPS fixes and improvements for October 2018 | expand

Commit Message

Aleksandar Markovic Oct. 11, 2018, 11:22 a.m. UTC 
From: Yongbok Kim <yongbok.kim@mips.com>

Add CPO MemoryMapID register. It is used by Global TLB Invalidate
instruction (GINVT).

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h      | 1 +
 target/mips/internal.h | 1 +
 target/mips/machine.c  | 4 ++++
 3 files changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 10c3813..77c6355 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -252,6 +252,7 @@  struct CPUMIPSState {
 #define CP0GN_VPId 0
     target_ulong CP0_Context;
     target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
+    int32_t CP0_MemoryMapID;
     int32_t CP0_PageMask;
     int32_t CP0_PageGrain_rw_bitmask;
     int32_t CP0_PageGrain;
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 2898bfc..6888a06 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -91,6 +91,7 @@  struct r4k_tlb_t {
     target_ulong VPN;
     uint32_t PageMask;
     uint16_t ASID;
+    uint32_t MMID;
     unsigned int G:1;
     unsigned int C0:3;
     unsigned int C1:3;
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 0ef9b71..8e34b8c 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -136,6 +136,7 @@  static int get_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field)
     qemu_get_betls(f, &v->VPN);
     qemu_get_be32s(f, &v->PageMask);
     qemu_get_be16s(f, &v->ASID);
+    qemu_get_be32s(f, &v->MMID);
     qemu_get_be16s(f, &flags);
     v->G = (flags >> 10) & 1;
     v->C0 = (flags >> 7) & 3;
@@ -161,6 +162,7 @@  static int put_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field,
     r4k_tlb_t *v = pv;
 
     uint16_t asid = v->ASID;
+    uint32_t mmid = v->MMID;
     uint16_t flags = ((v->EHINV << 15) |
                       (v->RI1 << 14) |
                       (v->RI0 << 13) |
@@ -177,6 +179,7 @@  static int put_tlb(QEMUFile *f, void *pv, size_t size, VMStateField *field,
     qemu_put_betls(f, &v->VPN);
     qemu_put_be32s(f, &v->PageMask);
     qemu_put_be16s(f, &asid);
+    qemu_put_be32s(f, &mmid);
     qemu_put_be16s(f, &flags);
     qemu_put_be64s(f, &v->PFN[0]);
     qemu_put_be64s(f, &v->PFN[1]);
@@ -251,6 +254,7 @@  const VMStateDescription vmstate_mips_cpu = {
         VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU),
         VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU),
         VMSTATE_UINTTL(env.CP0_Context, MIPSCPU),
+        VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU),
         VMSTATE_INT32(env.CP0_PageMask, MIPSCPU),
         VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU),
         VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU),