diff mbox series

[v4,07/22] target/mips: Add CPO PWCtl register

Message ID 1539256947-22807-8-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series Misc MIPS fixes and improvements for October 2018 | expand

Commit Message

Aleksandar Markovic Oct. 11, 2018, 11:22 a.m. UTC 
From: Yongbok Kim <yongbok.kim@mips.com>

Add PWCtl register (CP0 Register 5, Select 6).

The PWCtl register configures hardware page table walking for TLB
refills.

This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1. It contains following
fields:

PWEn   (31)   - Hardware Page Table walker enable
DPH    (7)    - Dual Page format of Huge Page support
HugePg (6)    - Huge Page PTE supported in Directory levels
PSn    (5..0) - Bit position of PTEvld in Huge Page PTE

Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/cpu.h       |  5 +++++
 target/mips/helper.h    |  1 +
 target/mips/machine.c   |  1 +
 target/mips/op_helper.c | 10 ++++++++++
 target/mips/translate.c | 20 ++++++++++++++++++++
 5 files changed, 37 insertions(+)

Comments

Aleksandar Markovic Oct. 12, 2018, 1:29 p.m. UTC | #1 
> From: Yongbok Kim <yongbok.kim@mips.com>
> 
> Add PWCtl register (CP0 Register 5, Select 6).

Please bump version_id and minimum_version_id of vmstate_mips_cpu in machine.c.

Other than this:

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
diff mbox series

Patch

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index a6abd1f..5e45e97 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -304,6 +304,11 @@  struct CPUMIPSState {
 #define CP0PS_PTW  6     /* 11..6  */
 #define CP0PS_PTEW 0     /*  5..0  */
     int32_t CP0_Wired;
+    int32_t CP0_PWCtl;
+#define CP0PC_PWEN      31
+#define CP0PC_DPH       7
+#define CP0PC_HUGEPG    6
+#define CP0PC_PSN       0     /*  5..0  */
     int32_t CP0_SRSConf0_rw_bitmask;
     int32_t CP0_SRSConf0;
 #define CP0SRSC0_M	31
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 169890a..c23e4e5 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -129,6 +129,7 @@  DEF_HELPER_2(mtc0_srsconf2, void, env, tl)
 DEF_HELPER_2(mtc0_srsconf3, void, env, tl)
 DEF_HELPER_2(mtc0_srsconf4, void, env, tl)
 DEF_HELPER_2(mtc0_hwrena, void, env, tl)
+DEF_HELPER_2(mtc0_pwctl, void, env, tl)
 DEF_HELPER_2(mtc0_count, void, env, tl)
 DEF_HELPER_2(mtc0_entryhi, void, env, tl)
 DEF_HELPER_2(mttc0_entryhi, void, env, tl)
diff --git a/target/mips/machine.c b/target/mips/machine.c
index 31e3d95..67a85a0 100644
--- a/target/mips/machine.c
+++ b/target/mips/machine.c
@@ -260,6 +260,7 @@  const VMStateDescription vmstate_mips_cpu = {
         VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU),
         VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU),
         VMSTATE_INT32(env.CP0_Wired, MIPSCPU),
+        VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU),
         VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU),
         VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU),
         VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU),
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 0986baf..e649bd0 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -1524,6 +1524,16 @@  void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
 }
 
+void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
+{
+#ifdef TARGET_MIPS64
+    /* PWEn = 0. Hardware page table walking is not implemented. */
+    env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
+#else
+    env->CP0_PWCtl = (arg1 & 0x800000FF);
+#endif
+}
+
 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
 {
     uint32_t mask = 0x0000000F;
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ef38be9..f669d48 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -5598,6 +5598,11 @@  static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
             rn = "SRSConf4";
             break;
+        case 6:
+            check_pw(ctx);
+            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
+            rn = "PWCtl";
+            break;
         default:
             goto cp0_unimplemented;
         }
@@ -6314,6 +6319,11 @@  static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_helper_mtc0_srsconf4(cpu_env, arg);
             rn = "SRSConf4";
             break;
+        case 6:
+            check_pw(ctx);
+            gen_helper_mtc0_pwctl(cpu_env, arg);
+            rn = "PWCtl";
+            break;
         default:
             goto cp0_unimplemented;
         }
@@ -7039,6 +7049,11 @@  static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
             rn = "SRSConf4";
             break;
+        case 6:
+            check_pw(ctx);
+            gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
+            rn = "PWCtl";
+            break;
         default:
             goto cp0_unimplemented;
         }
@@ -7737,6 +7752,11 @@  static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
             gen_helper_mtc0_srsconf4(cpu_env, arg);
             rn = "SRSConf4";
             break;
+        case 6:
+            check_pw(ctx);
+            gen_helper_mtc0_pwctl(cpu_env, arg);
+            rn = "PWCtl";
+            break;
         default:
             goto cp0_unimplemented;
         }