[v2,01/12] net: cadence_gem: Disable TSU feature bit

Message ID	20181011021931.4249-2-edgar.iglesias@gmail.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> To: qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Thu, 11 Oct 2018 04:19:20 +0200 Message-Id: <20181011021931.4249-2-edgar.iglesias@gmail.com> In-Reply-To: <20181011021931.4249-1-edgar.iglesias@gmail.com> References: <20181011021931.4249-1-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v2 01/12] net: cadence_gem: Disable TSU feature bit Precedence: list Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org, edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com, philmd@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	arm: Add first models of Xilinx Versal SoC \| expand [v2,00/12] arm: Add first models of Xilinx Versal SoC [v2,01/12] net: cadence_gem: Disable TSU feature bit [v2,02/12] net: cadence_gem: Announce availability of priority queues [v2,04/12] net: cadence_gem: Add macro with max number of descriptor words [v2,05/12] net: cadence_gem: Add support for extended descriptors [v2,06/12] net: cadence_gem: Add support for selecting the DMA MemoryRegion [v2,07/12] net: cadence_gem: Implement support for 64bit descriptor addresses [v2,08/12] net: cadence_gem: Announce 64bit addressing support [v2,09/12] target-arm: powerctl: Enable HVC when starting CPUs to EL2 [v2,10/12] target/arm: Add the Cortex-A72 [v2,11/12] hw/arm: versal: Add a model of Xilinx Versal SoC [v2,12/12] hw/arm: versal: Add a virtual Xilinx Versal board

Message ID

20181011021931.4249-2-edgar.iglesias@gmail.com

State

New

Headers

From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org,
	qemu-arm@nongnu.org
Date: Thu, 11 Oct 2018 04:19:20 +0200
Message-Id: <20181011021931.4249-2-edgar.iglesias@gmail.com>
In-Reply-To: <20181011021931.4249-1-edgar.iglesias@gmail.com>
References: <20181011021931.4249-1-edgar.iglesias@gmail.com>
Subject: [Qemu-devel] [PATCH v2 01/12] net: cadence_gem: Disable TSU feature
	bit
Precedence: list
Cc: figlesia@xilinx.com, peter.maydell@linaro.org, sstabellini@kernel.org,
	edgar.iglesias@xilinx.com, sai.pavan.boddu@xilinx.com,
	frasse.iglesias@gmail.com, alistair@alistair23.me,
	richard.henderson@linaro.org, frederic.konrad@adacore.com,
	philmd@redhat.com
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

arm: Add first models of Xilinx Versal SoC | expand

Commit Message

Edgar E. Iglesias Oct. 11, 2018, 2:19 a.m. UTC

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Disable the Timestamping Unit feature bit since QEMU does not
yet support it. This allows guest SW to correctly probe for
its existance.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/net/cadence_gem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index 0fa4b0dc44..e560b7a142 100644
--- a/hw/net/cadence_gem.c
+++ b/hw/net/cadence_gem.c
@@ -1228,7 +1228,7 @@  static void gem_reset(DeviceState *d)
     s->regs[GEM_MODID] = s->revision;
     s->regs[GEM_DESCONF] = 0x02500111;
     s->regs[GEM_DESCONF2] = 0x2ab13fff;
-    s->regs[GEM_DESCONF5] = 0x002f2145;
+    s->regs[GEM_DESCONF5] = 0x002f2045;
     s->regs[GEM_DESCONF6] = 0x00000200;
 
     /* Set MAC address */

[v2,01/12] net: cadence_gem: Disable TSU feature bit

Commit Message

Patch