[rs6000] testcases for vec_mergee and vec_mergeo

Message ID 1539184428.16697.54.camel@brimstone.rchland.ibm.com
State New
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  • [rs6000] testcases for vec_mergee and vec_mergeo
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Commit Message

Will Schmidt Oct. 10, 2018, 3:13 p.m.
Hi,
    
Some additional testcases to exercise the vec_mergee and
vec_mergeo intrinsics.

Tested across assorted power linux platforms.  OK for trunk?

Thanks
-Will
    
[testsuite]
    
2018-10-10  Will Schmidt  <will_schmidt@vnet.ibm.com>

	* gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c: New.
	* gcc.target/powerpc/fold-vec-mergeeo-int.c: New.
	* gcc.target/powerpc/fold-vec-mergeeo-longlong.c: New.

Comments

Segher Boessenkool Oct. 10, 2018, 3:35 p.m. | #1
Hi Will,

On Wed, Oct 10, 2018 at 10:13:48AM -0500, Will Schmidt wrote:
> Some additional testcases to exercise the vec_mergee and
> vec_mergeo intrinsics.
> 
> Tested across assorted power linux platforms.  OK for trunk?

Sure, that looks fine, okay for trunk.  Thanks!  One little thing:

> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_p8vector_ok } */
> +/* { dg-options "-mcpu=power8 -mpower8-vector " } */

-mpower8-vector is redundant with -mcpu=power8.

It's still correct of course, you don't need to change this, just FYI.

Thanks!


Segher

Patch

diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c
new file mode 100644
index 0000000..d711848
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-floatdouble.c
@@ -0,0 +1,46 @@ 
+/* Verify that overloaded built-ins for vec_splat with float and
+   double inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mcpu=power8 -mpower8-vector " } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+/*
+	vector float foo = vec_mergee (vector float, vector float);
+	vector float foo = vec_mergeo (vector float, vector float);
+	vector double foo = vec_mergee (vector double , vector double);
+	vector double foo = vec_mergeo (vector double , vector double);
+*/
+
+vector float
+testf_ee (vector float vf1, vector float vf2)
+{
+  return vec_mergee (vf1, vf2);
+}
+
+vector float
+testf_eo (vector float vf1, vector float vf2)
+{
+  return vec_mergeo (vf1, vf2);
+}
+
+vector double
+testd_ee ( vector double vd1, vector double vd2)
+{
+  return vec_mergee (vd1, vd2);
+}
+
+vector double
+testd_eo ( vector double vd1, vector double vd2)
+{
+  return vec_mergeo (vd1, vd2);
+}
+/* Doubles will generate vmrg*w instructions.  */
+/* { dg-final { scan-assembler-times "vmrgow" 1 } } */
+/* { dg-final { scan-assembler-times "vmrgew" 1 } } */
+/* Floats will generate some number of xxpermdi instructions.  Ensure we get at least one. */
+/* { dg-final { scan-assembler "xxpermdi" } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c
new file mode 100644
index 0000000..565f3ac
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-int.c
@@ -0,0 +1,48 @@ 
+/* Verify that overloaded built-ins for vec_mergee and vec_mergeo with int
+ inputs produce the right codegen.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+vector bool int
+testbi_ee (vector bool int v1, vector bool int v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector signed int
+testsi_ee (vector signed int v1, vector signed int v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector unsigned int
+testui_ee (vector unsigned int v1, vector unsigned int v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector bool int
+testbi_eo (vector bool int v1, vector bool int v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+vector signed int
+testsi_eo (vector signed int v1, vector signed int v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+vector unsigned int
+testui_eo (vector unsigned int v1, vector unsigned int v2)
+{
+  return vec_mergeo (v1, v2);
+}
+/* { dg-final { scan-assembler-times "vmrgew" 3 } } */
+/* { dg-final { scan-assembler-times "vmrgow" 3 } } */
+
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c
new file mode 100644
index 0000000..a5e59bf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mergeeo-longlong.c
@@ -0,0 +1,52 @@ 
+/* Verify that overloaded built-ins for vec_mergee and vec_mergeo
+ with long long inputs produce the right codegen.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mpower8-vector -mcpu=power8" } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */
+
+#include <altivec.h>
+
+
+vector bool long long
+testbi_ee (vector bool long long v1, vector bool long long v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector bool long long
+testbi_eo (vector bool long long v1, vector bool long long v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+vector signed long long
+testsi_ee (vector signed long long v1, vector signed long long v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector signed long long
+testsi_eo (vector signed long long v1, vector signed long long v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+vector unsigned long long
+testui_ee (vector unsigned long long v1, vector unsigned long long v2)
+{
+  return vec_mergee (v1, v2);
+}
+
+vector unsigned long long
+testui_eo (vector unsigned long long v1, vector unsigned long long v2)
+{
+  return vec_mergeo (v1, v2);
+}
+
+/* long long ...   */
+/* vec_mergee and vec_mergeo codegen will consist of some number of
+ xxpermdi instructions that will vary.  Ensure we get at least one. */
+/* { dg-final { scan-assembler "xxpermdi" } } */
+