From patchwork Wed Jun 1 14:16:00 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Brook X-Patchwork-Id: 98192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id B3AB8B6F7D for ; Thu, 2 Jun 2011 00:16:23 +1000 (EST) Received: (qmail 25289 invoked by alias); 1 Jun 2011 14:16:20 -0000 Received: (qmail 25266 invoked by uid 22791); 1 Jun 2011 14:16:18 -0000 X-SWARE-Spam-Status: No, hits=-0.4 required=5.0 tests=AWL, BAYES_50, TW_IW, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from mail.codesourcery.com (HELO mail.codesourcery.com) (38.113.113.100) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Wed, 01 Jun 2011 14:16:04 +0000 Received: (qmail 28277 invoked from network); 1 Jun 2011 14:16:04 -0000 Received: from unknown (HELO wren.localnet) (paul@127.0.0.2) by mail.codesourcery.com with ESMTPA; 1 Jun 2011 14:16:04 -0000 From: Paul Brook To: gcc-patches@gcc.gnu.org Subject: ARM Cortex-R5 support Date: Wed, 1 Jun 2011 15:16:00 +0100 User-Agent: KMail/1.13.7 (Linux/2.6.38-2-amd64; KDE/4.6.3; x86_64; ; ) MIME-Version: 1.0 Message-Id: <201106011516.01973.paul@codesourcery.com> Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The attached patch adds support from the ARM Cortex-R5 cpu core. For compiler purposes this is basically the same as the Cortex-R4, except it supports the integer division instructions in both ARM and Thumb mode. The Cortex-A15 also supports this, so I've enabled it there at the same time. Tested on arm-none-eabi Applied to SVN head. Paul 2011-06-01 Paul Brook gcc/ * config/arm/arm-cores.def: Add cortex-r5. Add DIV flags to Cortex-A15. * config/arm/arm-tune.md: Regenerate. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm.c (FL_DIV): Rename... (FL_THUMB_DIV): ... to this. (FL_ARM_DIV): Define. (FL_FOR_ARCH7R, FL_FOR_ARCH7M): Use FL_THUMB_DIV. (arm_arch_hwdiv): Remove. (arm_arch_thumb_hwdiv, arm_arch_arm_hwdiv): New variables. (arm_issue_rate): Add cortexr5. * config/arm/arm.h (TARGET_CPU_CPP_BUILTINS): Set __ARM_ARCH_EXT_IDIV__. (TARGET_IDIV): Define. (arm_arch_hwdiv): Remove. (arm_arch_arm_hwdiv, arm_arch_thumb_hwdiv): New prototypes. * config/arm/arm.md (tune_cortexr4): Add cortexr5. (divsi3, udivsi3): New patterns. * config/arm/thumb2.md (divsi3, udivsi3): Remove. * doc/invoke.texi: Document ARM -mcpu=cortex-r5 Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 174524) +++ gcc/doc/invoke.texi (working copy) @@ -10241,7 +10241,8 @@ assembly code. Permissible names are: @ @samp{arm1136j-s}, @samp{arm1136jf-s}, @samp{mpcore}, @samp{mpcorenovfp}, @samp{arm1156t2-s}, @samp{arm1156t2f-s}, @samp{arm1176jz-s}, @samp{arm1176jzf-s}, @samp{cortex-a5}, @samp{cortex-a8}, @samp{cortex-a9}, @samp{cortex-a15}, -@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-m4}, @samp{cortex-m3}, +@samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5}, +@samp{cortex-m4}, @samp{cortex-m3}, @samp{cortex-m1}, @samp{cortex-m0}, @samp{xscale}, @samp{iwmmxt}, @samp{iwmmxt2}, @samp{ep9312}. Index: gcc/config/arm/arm.c =================================================================== --- gcc/config/arm/arm.c (revision 174524) +++ gcc/config/arm/arm.c (working copy) @@ -662,12 +662,13 @@ static int thumb_call_reg_needed; #define FL_THUMB2 (1 << 16) /* Thumb-2. */ #define FL_NOTM (1 << 17) /* Instructions not present in the 'M' profile. */ -#define FL_DIV (1 << 18) /* Hardware divide. */ +#define FL_THUMB_DIV (1 << 18) /* Hardware divide (Thumb mode). */ #define FL_VFPV3 (1 << 19) /* Vector Floating Point V3. */ #define FL_NEON (1 << 20) /* Neon instructions. */ #define FL_ARCH7EM (1 << 21) /* Instructions present in the ARMv7E-M architecture. */ #define FL_ARCH7 (1 << 22) /* Architecture 7. */ +#define FL_ARM_DIV (1 << 23) /* Hardware divide (ARM mode). */ #define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ @@ -694,8 +695,8 @@ static int thumb_call_reg_needed; #define FL_FOR_ARCH6M (FL_FOR_ARCH6 & ~FL_NOTM) #define FL_FOR_ARCH7 ((FL_FOR_ARCH6T2 & ~FL_NOTM) | FL_ARCH7) #define FL_FOR_ARCH7A (FL_FOR_ARCH7 | FL_NOTM | FL_ARCH6K) -#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_DIV) -#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_DIV) +#define FL_FOR_ARCH7R (FL_FOR_ARCH7A | FL_THUMB_DIV) +#define FL_FOR_ARCH7M (FL_FOR_ARCH7 | FL_THUMB_DIV) #define FL_FOR_ARCH7EM (FL_FOR_ARCH7M | FL_ARCH7EM) /* The bits in this mask specify which @@ -781,7 +782,8 @@ int arm_cpp_interwork = 0; int arm_arch_thumb2; /* Nonzero if chip supports integer division instruction. */ -int arm_arch_hwdiv; +int arm_arch_arm_hwdiv; +int arm_arch_thumb_hwdiv; /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we must report the mode of the memory reference from @@ -1449,7 +1451,8 @@ arm_option_override (void) arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; - arm_arch_hwdiv = (insn_flags & FL_DIV) != 0; + arm_arch_thumb_hwdiv = (insn_flags & FL_THUMB_DIV) != 0; + arm_arch_arm_hwdiv = (insn_flags & FL_ARM_DIV) != 0; arm_tune_cortex_a9 = (arm_tune == cortexa9) != 0; /* If we are not using the default (ARM mode) section anchor offset @@ -23019,6 +23022,7 @@ arm_issue_rate (void) { case cortexr4: case cortexr4f: + case cortexr5: case cortexa5: case cortexa8: case cortexa9: Index: gcc/config/arm/thumb2.md =================================================================== --- gcc/config/arm/thumb2.md (revision 174524) +++ gcc/config/arm/thumb2.md (working copy) @@ -779,26 +779,6 @@ (define_insn "*thumb2_addsi_short" (set_attr "length" "2")] ) -(define_insn "divsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (div:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "s_register_operand" "r")))] - "TARGET_THUMB2 && arm_arch_hwdiv" - "sdiv%?\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "insn" "sdiv")] -) - -(define_insn "udivsi3" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (udiv:SI (match_operand:SI 1 "s_register_operand" "r") - (match_operand:SI 2 "s_register_operand" "r")))] - "TARGET_THUMB2 && arm_arch_hwdiv" - "udiv%?\t%0, %1, %2" - [(set_attr "predicable" "yes") - (set_attr "insn" "udiv")] -) - (define_insn "*thumb2_subsi_short" [(set (match_operand:SI 0 "low_register_operand" "=l") (minus:SI (match_operand:SI 1 "low_register_operand" "l") Index: gcc/config/arm/arm.h =================================================================== --- gcc/config/arm/arm.h (revision 174524) +++ gcc/config/arm/arm.h (working copy) @@ -101,6 +101,8 @@ extern char arm_arch_name[]; builtin_define ("__ARM_PCS"); \ builtin_define ("__ARM_EABI__"); \ } \ + if (TARGET_IDIV) \ + builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ } while (0) #include "config/arm/arm-opts.h" @@ -290,6 +292,10 @@ extern void (*arm_lang_output_object_att /* Nonzero if this chip supports ldrex{bhd} and strex{bhd}. */ #define TARGET_HAVE_LDREXBHD ((arm_arch6k && TARGET_ARM) || arm_arch7) +/* Nonzero if integer division instructions supported. */ +#define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ + || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) + /* True iff the full BPABI is being used. If TARGET_BPABI is true, then TARGET_AAPCS_BASED must be true -- but the converse does not hold. TARGET_BPABI implies the use of the BPABI runtime library, @@ -430,8 +436,11 @@ extern int arm_cpp_interwork; /* Nonzero if chip supports Thumb 2. */ extern int arm_arch_thumb2; -/* Nonzero if chip supports integer division instruction. */ -extern int arm_arch_hwdiv; +/* Nonzero if chip supports integer division instruction in ARM mode. */ +extern int arm_arch_arm_hwdiv; + +/* Nonzero if chip supports integer division instruction in Thumb mode. */ +extern int arm_arch_thumb_hwdiv; #ifndef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_APCS_FRAME) Index: gcc/config/arm/arm-cores.def =================================================================== --- gcc/config/arm/arm-cores.def (revision 174524) +++ gcc/config/arm/arm-cores.def (working copy) @@ -127,9 +127,10 @@ ARM_CORE("arm1156t2f-s", arm1156t2fs, ARM_CORE("cortex-a5", cortexa5, 7A, FL_LDSCHED, 9e) ARM_CORE("cortex-a8", cortexa8, 7A, FL_LDSCHED, 9e) ARM_CORE("cortex-a9", cortexa9, 7A, FL_LDSCHED, cortex_a9) -ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED, 9e) +ARM_CORE("cortex-a15", cortexa15, 7A, FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV, 9e) ARM_CORE("cortex-r4", cortexr4, 7R, FL_LDSCHED, 9e) ARM_CORE("cortex-r4f", cortexr4f, 7R, FL_LDSCHED, 9e) +ARM_CORE("cortex-r5", cortexr5, 7R, FL_LDSCHED | FL_ARM_DIV, 9e) ARM_CORE("cortex-m4", cortexm4, 7EM, FL_LDSCHED, 9e) ARM_CORE("cortex-m3", cortexm3, 7M, FL_LDSCHED, 9e) ARM_CORE("cortex-m1", cortexm1, 6M, FL_LDSCHED, 9e) Index: gcc/config/arm/arm.md =================================================================== --- gcc/config/arm/arm.md (revision 174524) +++ gcc/config/arm/arm.md (working copy) @@ -496,7 +496,7 @@ (define_attr "ce_count" "" (const_int 1) (define_attr "tune_cortexr4" "yes,no" (const (if_then_else - (eq_attr "tune" "cortexr4,cortexr4f") + (eq_attr "tune" "cortexr4,cortexr4f,cortexr5") (const_string "yes") (const_string "no")))) @@ -3681,6 +3681,28 @@ (define_insn "extzv_t2" (set_attr "predicable" "yes")] ) + +;; Division instructions +(define_insn "divsi3" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (div:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_IDIV" + "sdiv%?\t%0, %1, %2" + [(set_attr "predicable" "yes") + (set_attr "insn" "sdiv")] +) + +(define_insn "udivsi3" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (udiv:SI (match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "s_register_operand" "r")))] + "TARGET_IDIV" + "udiv%?\t%0, %1, %2" + [(set_attr "predicable" "yes") + (set_attr "insn" "udiv")] +) + ;; Unary arithmetic insns