clk: at91: Fix division by zero in PLL recalc_rate()

Message ID fd2a1c19-8cb5-4db0-a2bb-6b0129162029@raritan.com
State New
Headers show
Series
  • clk: at91: Fix division by zero in PLL recalc_rate()
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Commit Message

Ronald WAHL Oct. 10, 2018, 10:31 a.m.
Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL
and DIV values") removed a check that prevents a division by zero. This
now causes a stacktrace when booting the kernel on a at91 platform if
the PLL DIV register contains zero. This commit reintroduces this check.

Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...")
Cc: <stable@vger.kernel.org>
Signed-off-by: Ronald Wahl <ronald.wahl@raritan.com>
---
 drivers/clk/at91/clk-pll.c | 3 +++
 1 file changed, 3 insertions(+)

--
2.17.1

Comments

Ludovic Desroches Oct. 10, 2018, 1:26 p.m. | #1
Hi Ronald,

On Wed, Oct 10, 2018 at 10:31:31AM +0000, Ronald WAHL wrote:
> Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL
> and DIV values") removed a check that prevents a division by zero. This
> now causes a stacktrace when booting the kernel on a at91 platform if
> the PLL DIV register contains zero. This commit reintroduces this check.
> 
> Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...")
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Ronald Wahl <ronald.wahl@raritan.com>
> ---
>  drivers/clk/at91/clk-pll.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
> index 72b6091eb7b9..dc7fbc796cb6 100644
> --- a/drivers/clk/at91/clk-pll.c
> +++ b/drivers/clk/at91/clk-pll.c
> @@ -133,6 +133,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
>  {
>  struct clk_pll *pll = to_clk_pll(hw);
> 
> +if (!pll->div || !pll->mul)
> +return 0;
> +
>  return (parent_rate / pll->div) * (pll->mul + 1);
>  }

Weird indentation here. Patch doesn't apply.

Otherwise,
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>

Regards

Ludovic
Ronald WAHL Oct. 10, 2018, 1:43 p.m. | #2
Hi,

argh, this is probably caused by the mail server of my company. I'll
resent the patch over a different provider hoping it works then. Sorry.

- ron

On 10.10.18 15:26, Ludovic Desroches wrote:
> Hi Ronald,
>
> On Wed, Oct 10, 2018 at 10:31:31AM +0000, Ronald WAHL wrote:
>> Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL
>> and DIV values") removed a check that prevents a division by zero. This
>> now causes a stacktrace when booting the kernel on a at91 platform if
>> the PLL DIV register contains zero. This commit reintroduces this check.
>>
>> Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...")
>> Cc: <stable@vger.kernel.org>
>> Signed-off-by: Ronald Wahl <ronald.wahl@raritan.com>
>> ---
>>   drivers/clk/at91/clk-pll.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
>> index 72b6091eb7b9..dc7fbc796cb6 100644
>> --- a/drivers/clk/at91/clk-pll.c
>> +++ b/drivers/clk/at91/clk-pll.c
>> @@ -133,6 +133,9 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
>>   {
>>   struct clk_pll *pll = to_clk_pll(hw);
>>
>> +if (!pll->div || !pll->mul)
>> +return 0;
>> +
>>   return (parent_rate / pll->div) * (pll->mul + 1);
>>   }
>
> Weird indentation here. Patch doesn't apply.
>
> Otherwise,
> Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
>
> Regards
>
> Ludovic
>

--
Ronald Wahl
Principal Software Engineer, Raritan Deutschland GmbH
Kornmarkt 7, 08056 Zwickau, Germany
Amtsgericht Chemnitz HRB 23605, Geschäftsführung: Ralf Ploenes

Patch

diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 72b6091eb7b9..dc7fbc796cb6 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -133,6 +133,9 @@  static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
 {
 struct clk_pll *pll = to_clk_pll(hw);

+if (!pll->div || !pll->mul)
+return 0;
+
 return (parent_rate / pll->div) * (pll->mul + 1);
 }