| Message ID | 20181007142045.26036-1-aford173@gmail.com |
|---|---|
| State | Accepted |
| Commit | 169eb191355ec4c5b5b7335ddaf8b73a167a698b |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [U-Boot] ARM: omap3_logic.c: Optimize DDR timings based on OMAP35 or 36/37 | expand |
On Sun, Oct 07, 2018 at 09:20:45AM -0500, Adam Ford wrote: > The default timings are assumming an OMAP36 / AM37 / DM37, but > the OMAP35 controller is a bit slower, so DDR may operate out of > spec when under stress. This patch checks the processor type and > sets the DDR timings according to processor type. > > Fixes: 5ad4212ce0d5 ("ARM: DTS: Add Logic PD OMAP35/DM37 SOM-LV > and OMAP35 Torpedo") > > Signed-off-by: Adam Ford <aford173@gmail.com> > > diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c > index 4507b1ed99..0b827355a8 100644 Applied to u-boot/master, thanks!
diff --git a/board/logicpd/omap3som/omap3logic.c b/board/logicpd/omap3som/omap3logic.c index 4507b1ed99..0b827355a8 100644 --- a/board/logicpd/omap3som/omap3logic.c +++ b/board/logicpd/omap3som/omap3logic.c @@ -89,11 +89,21 @@ int spl_start_uboot(void) void get_board_mem_timings(struct board_sdrc_timings *timings) { timings->mr = MICRON_V_MR_165; - /* 256MB DDR */ - timings->mcfg = MICRON_V_MCFG_200(256 << 20); - timings->ctrla = MICRON_V_ACTIMA_200; - timings->ctrlb = MICRON_V_ACTIMB_200; - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + + if (get_cpu_family() == CPU_OMAP36XX) { + /* 200 MHz works for OMAP36/DM37 */ + /* 256MB DDR */ + timings->mcfg = MICRON_V_MCFG_200(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_200; + timings->ctrlb = MICRON_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } else { + /* 165 MHz works for OMAP35 */ + timings->mcfg = MICRON_V_MCFG_165(256 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } } #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE + 0x7c)
The default timings are assumming an OMAP36 / AM37 / DM37, but the OMAP35 controller is a bit slower, so DDR may operate out of spec when under stress. This patch checks the processor type and sets the DDR timings according to processor type. Fixes: 5ad4212ce0d5 ("ARM: DTS: Add Logic PD OMAP35/DM37 SOM-LV and OMAP35 Torpedo") Signed-off-by: Adam Ford <aford173@gmail.com>