From patchwork Tue May 31 10:59:05 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: jj X-Patchwork-Id: 98014 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BBEF4B6F72 for ; Tue, 31 May 2011 21:45:10 +1000 (EST) Received: from localhost ([::1]:43516 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRNNh-00027Q-Uo for incoming@patchwork.ozlabs.org; Tue, 31 May 2011 07:45:05 -0400 Received: from eggs.gnu.org ([140.186.70.92]:48974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRNNV-00027H-SW for qemu-devel@nongnu.org; Tue, 31 May 2011 07:44:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QRNNS-0007v0-5A for qemu-devel@nongnu.org; Tue, 31 May 2011 07:44:53 -0400 Received: from m13-173.163.com ([220.181.13.173]:54162) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRNNR-0007qg-17 for qemu-devel@nongnu.org; Tue, 31 May 2011 07:44:50 -0400 Received: from jjjjjj00jj ( [114.80.244.146] ) by ajax-webmail-wmsvr173 (Coremail) ; Tue, 31 May 2011 18:59:05 +0800 (CST) Date: Tue, 31 May 2011 18:59:05 +0800 (CST) From: jj To: qemu-devel Message-ID: <480751ab.cb66.13045b4f796.Coremail.jjjjjj00jj@163.com> In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [114.80.244.146] X-Priority: 3 X-Mailer: Coremail Webmail Server Version SP_ntes V3.5 build 110420(13372.3725.3724) Copyright (c) 2002-2011 www.mailtech.cn 163com X-CM-TRANSID: rcGowKCLzt_5yeRNKUMmAA--.9074W X-CM-SenderInfo: hmmmyybmqqyyi6rwjhhfrp/1tbi6wNQB02-0qVufgABsr X-Coremail-Antispam: 1U5529EdanIXcx71UUUUU7vcSsGvfC2KfnxnUU== X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6, seldom 2.4 (older, 4) X-Received-From: 220.181.13.173 Subject: Re: [Qemu-devel] [PATCH uq/master V3] kvm: Add CPUID support for VIA CPU X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: BrillyWu@viatech.com.cn When KVM is running on VIA CPU with host cpu's model, the feautures of VIA CPU will be passed into kvm guest by calling the CPUID instruction for Centaur. Signed-off-by: BrillyWu Signed-off-by: KaryJin --- target-i386/cpu.h | 7 +++++++ target-i386/cpuid.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++-- target-i386/kvm.c | 15 +++++++++++++++ 3 files changed, 73 insertions(+), 2 deletions(-) --- a/target-i386/cpu.h 2011-05-30 16:20:57.261342707 +0800 +++ b/target-i386/cpu.h 2011-05-31 16:49:43.617252109 +0800 @@ -441,6 +441,10 @@ #define CPUID_VENDOR_AMD_2 0x69746e65 /* "enti" */ #define CPUID_VENDOR_AMD_3 0x444d4163 /* "cAMD" */ +#define CPUID_VENDOR_VIA_1 0x746e6543 /* "Cent" */ +#define CPUID_VENDOR_VIA_2 0x48727561 /* "aurH" */ +#define CPUID_VENDOR_VIA_3 0x736c7561 /* "auls" */ + #define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ #define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ @@ -730,6 +734,9 @@ typedef struct CPUX86State { uint32_t cpuid_ext3_features; uint32_t cpuid_apic_id; int cpuid_vendor_override; + /* Store the results of Centaur's CPUID instructions */ + uint32_t cpuid_xlevel2; + uint32_t cpuid_ext4_features; /* MTRRs */ uint64_t mtrr_fixed[11]; --- a/target-i386/cpuid.c 2011-05-30 16:20:57.261342707 +0800 +++ b/target-i386/cpuid.c 2011-05-31 16:47:55.077252267 +0800 @@ -230,6 +230,9 @@ typedef struct x86_def_t { char model_id[48]; int vendor_override; uint32_t flags; + /* Store the results of Centaur's CPUID instructions */ + uint32_t ext4_features; + uint32_t xlevel2; } x86_def_t; #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE) @@ -522,6 +525,18 @@ static int cpu_x86_fill_host(x86_def_t * cpu_x86_fill_model_id(x86_cpu_def->model_id); x86_cpu_def->vendor_override = 0; + /* Call Centaur's CPUID instruction. */ + if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 && + x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 && + x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) { + host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx); + if (eax >= 0xC0000001) { + /* Support VIA max extended level */ + x86_cpu_def->xlevel2 = eax; + host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx); + x86_cpu_def->ext4_features = edx; + } + } /* * Every SVM feature requires emulation support in KVM - so we can't just @@ -855,6 +870,8 @@ int cpu_x86_register (CPUX86State *env, env->cpuid_xlevel = def->xlevel; env->cpuid_kvm_features = def->kvm_features; env->cpuid_svm_features = def->svm_features; + env->cpuid_ext4_features = def->ext4_features; + env->cpuid_xlevel2 = def->xlevel2; if (!kvm_enabled()) { env->cpuid_features &= TCG_FEATURES; env->cpuid_ext_features &= TCG_EXT_FEATURES; @@ -1035,8 +1052,18 @@ void cpu_x86_cpuid(CPUX86State *env, uin { /* test if maximum index reached */ if (index & 0x80000000) { - if (index > env->cpuid_xlevel) - index = env->cpuid_level; + if (index > env->cpuid_xlevel) { + if (env->cpuid_xlevel2 > 0) { + /* Handle the Centaur's CPUID instruction. */ + if (index > env->cpuid_xlevel2) { + index = env->cpuid_xlevel2; + } else if (index < 0xC0000000) { + index = env->cpuid_xlevel; + } + } else { + index = env->cpuid_xlevel; + } + } } else { if (index > env->cpuid_level) index = env->cpuid_level; @@ -1231,6 +1258,28 @@ void cpu_x86_cpuid(CPUX86State *env, uin *edx = 0; } break; + case 0xC0000000: + *eax = env->cpuid_xlevel2; + *ebx = 0; + *ecx = 0; + *edx = 0; + break; + case 0xC0000001: + /* Support for VIA CPU's CPUID instruction */ + *eax = env->cpuid_version; + *ebx = 0; + *ecx = 0; + *edx = env->cpuid_ext4_features; + break; + case 0xC0000002: + case 0xC0000003: + case 0xC0000004: + /* Reserved for the future, and now filled with zero */ + *eax = 0; + *ebx = 0; + *ecx = 0; + *edx = 0; + break; default: /* reserved values: zero */ *eax = 0; --- a/target-i386/kvm.c 2011-05-30 16:21:05.431342033 +0800 +++ b/target-i386/kvm.c 2011-05-30 10:16:03.284532914 +0800 @@ -482,6 +482,21 @@ int kvm_arch_init_vcpu(CPUState *env) cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); } + /* Call Centaur's CPUID instructions they are supported. */ + if (env->cpuid_xlevel2 > 0) { + env->cpuid_ext4_features &= + kvm_arch_get_supported_cpuid(env, 0xC0000001, 0, R_EDX); + cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); + + for (i = 0xC0000000; i <= limit; i++) { + c = &cpuid_data.entries[cpuid_i++]; + + c->function = i; + c->flags = 0; + cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); + } + } + cpuid_data.cpuid.nent = cpuid_i; #ifdef KVM_CAP_MCE