| Message ID | 20181004153321.34757-1-andriy.shevchenko@linux.intel.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v1,1/4] pinctrl: geminilake: Update pin list for B0 stepping | expand |
On Thu, Oct 04, 2018 at 06:33:18PM +0300, Andy Shevchenko wrote: > According to an updated pin list few names of the pins can be spelled better, > taking into account their primary functions. > > Thus, update a pin list to cover B0 stepping. > > Note, SPI numbering had been fixed even in A0 public documentation. > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
On Thu, Oct 4, 2018 at 5:33 PM Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > According to an updated pin list few names of the pins can be spelled better, > taking into account their primary functions. > > Thus, update a pin list to cover B0 stepping. > > Note, SPI numbering had been fixed even in A0 public documentation. > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> I applied patches 1, 3 and 4 to the pin control tree. Let's discuss patch 2. Yours, Linus Walleij
On Tue, Oct 16, 2018 at 09:19:18AM +0200, Linus Walleij wrote: > On Thu, Oct 4, 2018 at 5:33 PM Andy Shevchenko > <andriy.shevchenko@linux.intel.com> wrote: > > > According to an updated pin list few names of the pins can be spelled better, > > taking into account their primary functions. > > > > Thus, update a pin list to cover B0 stepping. > > > > Note, SPI numbering had been fixed even in A0 public documentation. > > > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > I applied patches 1, 3 and 4 to the pin control tree. > > Let's discuss patch 2. I tend to agree to what Mika said, i.e. until proven the opposite the vGPIO pins are subject to internal magic and no need to expose them. Thus, please, just drop patch 2, and thanks for applying the rest!
diff --git a/drivers/pinctrl/intel/pinctrl-geminilake.c b/drivers/pinctrl/intel/pinctrl-geminilake.c index 55c87d95207a..105881e5c042 100644 --- a/drivers/pinctrl/intel/pinctrl-geminilake.c +++ b/drivers/pinctrl/intel/pinctrl-geminilake.c @@ -58,16 +58,16 @@ static const struct pinctrl_pin_desc glk_northwest_pins[] = { PINCTRL_PIN(23, "GPIO_23"), PINCTRL_PIN(24, "GPIO_24"), PINCTRL_PIN(25, "GPIO_25"), - PINCTRL_PIN(26, "GPIO_26"), - PINCTRL_PIN(27, "GPIO_27"), - PINCTRL_PIN(28, "GPIO_28"), - PINCTRL_PIN(29, "GPIO_29"), - PINCTRL_PIN(30, "GPIO_30"), - PINCTRL_PIN(31, "GPIO_31"), - PINCTRL_PIN(32, "GPIO_32"), - PINCTRL_PIN(33, "GPIO_33"), - PINCTRL_PIN(34, "GPIO_34"), - PINCTRL_PIN(35, "GPIO_35"), + PINCTRL_PIN(26, "ISH_GPIO_0"), + PINCTRL_PIN(27, "ISH_GPIO_1"), + PINCTRL_PIN(28, "ISH_GPIO_2"), + PINCTRL_PIN(29, "ISH_GPIO_3"), + PINCTRL_PIN(30, "ISH_GPIO_4"), + PINCTRL_PIN(31, "ISH_GPIO_5"), + PINCTRL_PIN(32, "ISH_GPIO_6"), + PINCTRL_PIN(33, "ISH_GPIO_7"), + PINCTRL_PIN(34, "ISH_GPIO_8"), + PINCTRL_PIN(35, "ISH_GPIO_9"), PINCTRL_PIN(36, "GPIO_36"), PINCTRL_PIN(37, "GPIO_37"), PINCTRL_PIN(38, "GPIO_38"), @@ -195,12 +195,12 @@ static const struct pinctrl_pin_desc glk_north_pins[] = { PINCTRL_PIN(5, "LPSS_SPI_0_FS1"), PINCTRL_PIN(6, "LPSS_SPI_0_RXD"), PINCTRL_PIN(7, "LPSS_SPI_0_TXD"), - PINCTRL_PIN(8, "LPSS_SPI_1_CLK"), - PINCTRL_PIN(9, "LPSS_SPI_1_FS0"), - PINCTRL_PIN(10, "LPSS_SPI_1_FS1"), - PINCTRL_PIN(11, "LPSS_SPI_1_FS2"), - PINCTRL_PIN(12, "LPSS_SPI_1_RXD"), - PINCTRL_PIN(13, "LPSS_SPI_1_TXD"), + PINCTRL_PIN(8, "LPSS_SPI_2_CLK"), + PINCTRL_PIN(9, "LPSS_SPI_2_FS0"), + PINCTRL_PIN(10, "LPSS_SPI_2_FS1"), + PINCTRL_PIN(11, "LPSS_SPI_2_FS2"), + PINCTRL_PIN(12, "LPSS_SPI_2_RXD"), + PINCTRL_PIN(13, "LPSS_SPI_2_TXD"), PINCTRL_PIN(14, "FST_SPI_CS0_B"), PINCTRL_PIN(15, "FST_SPI_CS1_B"), PINCTRL_PIN(16, "FST_SPI_MOSI_IO0"), @@ -215,8 +215,8 @@ static const struct pinctrl_pin_desc glk_north_pins[] = { PINCTRL_PIN(25, "PMU_SLP_S3_B"), PINCTRL_PIN(26, "PMU_SLP_S4_B"), PINCTRL_PIN(27, "SUSPWRDNACK"), - PINCTRL_PIN(28, "EMMC_PWR_EN_B"), - PINCTRL_PIN(29, "PMU_AC_PRESENT"), + PINCTRL_PIN(28, "EMMC_DNX_PWR_EN_B"), + PINCTRL_PIN(29, "GPIO_105"), PINCTRL_PIN(30, "PMU_BATLOW_B"), PINCTRL_PIN(31, "PMU_RESETBUTTON_B"), PINCTRL_PIN(32, "PMU_SUSCLK"),
According to an updated pin list few names of the pins can be spelled better, taking into account their primary functions. Thus, update a pin list to cover B0 stepping. Note, SPI numbering had been fixed even in A0 public documentation. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- drivers/pinctrl/intel/pinctrl-geminilake.c | 36 +++++++++++----------- 1 file changed, 18 insertions(+), 18 deletions(-)