diff mbox series

[U-Boot,2/3] net: gem: Do not setup any clock for Xilinx SoC Versal

Message ID 7cf55de65927edc20c3aa37cc84c8404137b2cbb.1538546275.git.michal.simek@xilinx.com
State Deferred
Delegated to: Michal Simek
Headers show
Series Add support for new Xilinx Versal ACAPs | expand

Commit Message

Michal Simek Oct. 3, 2018, 5:57 a.m. UTC 
Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

 drivers/net/zynq_gem.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox series

Patch

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index f586f7de81a7..a1fee05dcb8f 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -461,6 +461,7 @@  static int zynq_gem_init(struct udevice *dev)
 		break;
 	}
 
+#if !defined(CONFIG_ARCH_VERSAL)
 	ret = clk_set_rate(&priv->clk, clk_rate);
 	if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) {
 		dev_err(dev, "failed to set tx clock rate\n");
@@ -472,6 +473,7 @@  static int zynq_gem_init(struct udevice *dev)
 		dev_err(dev, "failed to enable tx clock\n");
 		return ret;
 	}
+#endif
 
 	setbits_le32(&regs->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
 					ZYNQ_GEM_NWCTRL_TXEN_MASK);