From patchwork Sat May 28 04:50:55 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans-Peter Nilsson X-Patchwork-Id: 97765 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 40B4DB6F89 for ; Sat, 28 May 2011 14:51:14 +1000 (EST) Received: (qmail 29189 invoked by alias); 28 May 2011 04:51:11 -0000 Received: (qmail 29178 invoked by uid 22791); 28 May 2011 04:51:10 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL, BAYES_00, TW_EG, TW_TR X-Spam-Check-By: sourceware.org Received: from dair.pair.com (HELO dair.pair.com) (209.68.1.49) by sourceware.org (qpsmtpd/0.43rc1) with SMTP; Sat, 28 May 2011 04:50:55 +0000 Received: (qmail 13617 invoked by uid 20157); 28 May 2011 04:50:55 -0000 Received: from localhost (sendmail-bs@127.0.0.1) by localhost with SMTP; 28 May 2011 04:50:55 -0000 Date: Sat, 28 May 2011 00:50:55 -0400 (EDT) From: Hans-Peter Nilsson To: Vladimir Makarov cc: gcc-patches Subject: Re: RFA: another patch to solve PR49154 In-Reply-To: <4DDEBDB8.8000000@redhat.com> Message-ID: References: <4DDD7705.9020003@redhat.com> <4DDDB1EA.4080902@redhat.com> <4DDEBDB8.8000000@redhat.com> User-Agent: Alpine 2.00 (BSF 1167 2008-08-23) MIME-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Thu, 26 May 2011, Vladimir Makarov wrote: > On 05/26/2011 04:47 AM, Hans-Peter Nilsson wrote: > > On Wed, 25 May 2011, Vladimir Makarov wrote: > > It sounds like you're saying that "the narrowest register > > classes must be formed of registers for which there are trivial > > instructions to move between registers inside the class"? > > > No it is wrong. For example, SPARC FPCC (floating point control code > registers) should form a uniform class but there are no trvial insns to move > between registers inside the class. Yah, the code was tweaked to explicitly handle that case by excluding that condition for regclasses without subclasses. Is the following update ok with you (and doc maintainers)? It says what the code requires, and seems a simple enough rule. It also fills a documentation gap at the narrow end of the spectrum of register classes. (I'll update the CRIS port to fit.) If not, I can tweak the code instead (likely to also exclude the test for the narrowest code class to which a register belongs), and regtest that on the compilefarm machines, which IIRC should cover all the arch's you tested. But that'd require the code to keep handling non-minimal regclasses with side-conditions on moves as pressure classes, which seems less desirable to me, and judging from your willingness to patch a target the other way, I believe you agree. ;-) Tested by generating and inspecting dvi and info. gcc: * doc/tm.texi.in (Register Classes): Document rule for the narrowest register classes. * doc/tm.texi: Regenerate. brgds, H-P Index: tm.texi.in =================================================================== --- tm.texi.in (revision 174376) +++ tm.texi.in (working copy) @@ -2327,6 +2327,11 @@ constraints is through machine-dependent You can define such letters to correspond to various classes, then use them in operand constraints. +You must define the narrowest register class for a register so that +class either has no subclasses, or that for some mode, the move cost +between registers within the class are cheaper than moving a register +in the class to or from memory (@pxref{Costs}). + You should define a class for the union of two classes whenever some instruction allows both classes. For example, if an instruction allows either a floating point (coprocessor) register or a general register for a