diff mbox series

[v3,3/4] target/mips: Clean the 'insn_flags' namespace

Message ID 20180930214744.27580-4-f4bug@amsat.org
State New
Headers show
Series mips: Increase the insn_flags holder size and clean mips-defs.h | expand

Commit Message

Philippe Mathieu-Daudé Sept. 30, 2018, 9:47 p.m. UTC 
Let space available for the ASE_DSPR3 entry.

Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/mips-defs.h | 85 ++++++++++++++++++++++++-----------------
 1 file changed, 51 insertions(+), 34 deletions(-)

Comments

Aleksandar Markovic Oct. 17, 2018, 12:06 p.m. UTC | #1 
> From: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> on behalf of Philippe Mathieu-Daudé <f4bug@amsat.org>
> Subject: [PATCH v3 3/4] target/mips: Clean the 'insn_flags' namespace
>
> Let space available for the ASE_DSPR3 entry.
> 
> Suggested-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>

This patch will be included in the next MIPS queue with minor modifications.
diff mbox series

Patch

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index c0c5a98ef1..f9e99f866f 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -22,40 +22,57 @@ 
 #endif
 #endif
 
-/* Masks used to mark instructions to indicate which ISA level they
-   were introduced in. */
-#define		ISA_MIPS1	0x00000001
-#define		ISA_MIPS2	0x00000002
-#define		ISA_MIPS3	0x00000004
-#define		ISA_MIPS4	0x00000008
-#define		ISA_MIPS5	0x00000010
-#define		ISA_MIPS32	0x00000020
-#define		ISA_MIPS32R2	0x00000040
-#define		ISA_MIPS64	0x00000080
-#define		ISA_MIPS64R2	0x00000100
-#define   ISA_MIPS32R3  0x00000200
-#define   ISA_MIPS64R3  0x00000400
-#define   ISA_MIPS32R5  0x00000800
-#define   ISA_MIPS64R5  0x00001000
-#define   ISA_MIPS32R6  0x00002000
-#define   ISA_MIPS64R6  0x00004000
-#define   ISA_NANOMIPS32  0x00008000
-
-/* MIPS ASEs. */
-#define   ASE_MIPS16    0x00010000
-#define   ASE_MIPS3D    0x00020000
-#define   ASE_MDMX      0x00040000
-#define   ASE_DSP       0x00080000
-#define   ASE_DSPR2     0x00100000
-#define   ASE_MT        0x00200000
-#define   ASE_SMARTMIPS 0x00400000
-#define   ASE_MICROMIPS 0x00800000
-#define   ASE_MSA       0x01000000
-
-/* Chip specific instructions. */
-#define		INSN_LOONGSON2E  0x20000000
-#define		INSN_LOONGSON2F  0x40000000
-#define		INSN_VR54XX	0x80000000
+/*
+* insn_flags: mask used to mark instructions to indicate which ISA
+* level they were introduced in.
+*/
+
+/*
+ * bits 0-31 MIPS base instruction sets
+ */
+#define ISA_MIPS1         0x0000000000000001
+#define ISA_MIPS2         0x0000000000000002
+#define ISA_MIPS3         0x0000000000000004
+#define ISA_MIPS4         0x0000000000000008
+#define ISA_MIPS5         0x0000000000000010
+#define ISA_MIPS32        0x0000000000000020
+#define ISA_MIPS32R2      0x0000000000000040
+#define ISA_MIPS64        0x0000000000000080
+#define ISA_MIPS64R2      0x0000000000000100
+#define ISA_MIPS32R3      0x0000000000000200
+#define ISA_MIPS64R3      0x0000000000000400
+#define ISA_MIPS32R5      0x0000000000000800
+#define ISA_MIPS64R5      0x0000000000001000
+#define ISA_MIPS32R6      0x0000000000002000
+#define ISA_MIPS64R6      0x0000000000004000
+#define ISA_NANOMIPS32    0x0000000000008000
+
+/*
+ * bits 32-47 MIPS ASEs
+ */
+#define ASE_MIPS16        0x0000000100000000ULL
+#define ASE_MIPS3D        0x0000000200000000ULL
+#define ASE_MDMX          0x0000000400000000ULL
+#define ASE_DSP           0x0000000800000000ULL
+#define ASE_DSPR2         0x0000001000000000ULL
+#define ASE_MT            0x0000004000000000ULL
+#define ASE_SMARTMIPS     0x0000008000000000ULL
+#define ASE_MICROMIPS     0x0000010000000000ULL
+#define ASE_MSA           0x0000020000000000ULL
+
+/*
+ * bits 48-55 vendor-specific base instruction sets
+ */
+#define INSN_LOONGSON2E   0x0001000000000000ULL
+#define INSN_LOONGSON2F   0x0002000000000000ULL
+#define INSN_VR54XX       0x0004000000000000ULL
+
+/*
+ * bits 56-63 vendor-specific ASEs
+ *
+ * Example: Igenic ASE_MXU and ASE MXU2
+ */
+
 
 /* MIPS CPU defines. */
 #define		CPU_MIPS1	(ISA_MIPS1)