Patchwork PATCH: PR rtl-optimization/49114: Reload failed to handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const_int)))

Hi,

When reload gets:

(insn 588 587 589 28 (set (mem:DF (zero_extend:DI (plus:SI (subreg:SI
(reg/v/f:DI 182 [ b ]) 0) 
                    (const_int 8 [0x8]))) [4 MEM[base: b_96(D), index:
D.15020_278, step: 8, offset: 0B]+0 S8 A64])
        (reg:DF 340 [ D.14980 ])) spooles.c:291 106
{*movdf_internal_rex64}
     (expr_list:REG_DEAD (reg:DF 340 [ D.14980 ])
        (nil)))

it generates:

Reloads for insn # 588
Reload 0: reload_in (DI) = (reg/v/f:DI 182 [ b ]) 
        GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0) 
        reload_in_reg: (reg/v/f:DI 182 [ b ]) 
        reload_reg_rtx: (reg:DI 1 dx)
Reload 1: reload_in (DI) = (zero_extend:DI (plus:SI (subreg:SI
(reg/v/f:DI 182
[ b ]) 0)
                                                        (const_int 8
[0x8])))
        GENERAL_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0) 
        reload_in_reg: (zero_extend:DI (plus:SI (subreg:SI (reg/v/f:DI
182 [ b
]) 0)
                                                        (const_int 8
[0x8])))
        reload_reg_rtx: (reg:DI 1 dx)
Reload 2: reload_out (DF) = (mem:DF (zero_extend:DI (plus:SI (subreg:SI
(reg/v/f:DI 182 [ b ]) 0)
                                                            (const_int 8
[0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset:
0B]+0 S8
A64])
        NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
        reload_out_reg: (mem:DF (zero_extend:DI (plus:SI (subreg:SI
(reg/v/f:DI
182 [ b ]) 0)
                                                            (const_int 8
[0x8]))) [4 MEM[base: b_96(D), index: D.15020_278, step: 8, offset:
0B]+0 S8
A64])

leads to

(insn 1017 587 1020 34 (set (reg:DI 1 dx)
        (mem/c:DI (plus:DI (reg/f:DI 7 sp)
                (const_int 112 [0x70])) [5 %sfp+-208 S8 A64]))
spooles.c:291 62
{*movdi_internal_rex64}
     (nil))

(insn 1020 1017 1022 34 (set (reg:SI 1 dx)
        (const_int 8 [0x8])) spooles.c:291 64 {*movsi_internal}
     (nil))

(insn 1022 1020 1023 34 (set (reg:SI 1 dx)
        (reg:SI 1 dx)) spooles.c:291 64 {*movsi_internal}
     (nil))

(insn 1023 1022 1024 34 (set (reg:SI 1 dx)
        (plus:SI (reg:SI 1 dx)
            (const_int 8 [0x8]))) spooles.c:291 248 {*lea_1_x32}
     (expr_list:REG_EQUIV (plus:SI (subreg:SI (reg:DI 1 dx) 0)
            (const_int 8 [0x8]))
        (nil)))

(insn 1024 1023 588 34 (set (reg:DI 1 dx)
        (zero_extend:DI (reg:SI 1 dx))) spooles.c:291 112
{*zero_extendsidi2_rex64}
     (expr_list:REG_EQUIV (zero_extend:DI (plus:SI (subreg:SI (reg:DI 1
dx) 0)
                (const_int 8 [0x8])))
        (nil)))

(insn 588 1024 589 34 (set (mem:DF (reg:DI 1 dx) [4 MEM[base: b_96(D),
index:
D.15020_278, step: 8, offset: 0B]+0 S8 A64])
        (reg:DF 0 ax [orig:340 D.14980 ] [340])) spooles.c:291 106
{*movdf_internal_rex64}
     (nil))

gen_load has

     if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
          || (REG_P (op1)

For

(plus:SI (subreg:SI (reg/v/f:DI 182 [ b ]) 0) (const_int 8 [0x8]))

it swaps SUBREG and CONST_INT.  It leads to wrong code.  This patch
checks if OP0 is SUBREG before swapping.  OK for trunk?

Thanks.


H.J.
----
commit 1dfd59e2fbbea198d7f3e977b559b4f307b2a659
Author: H.J. Lu <hjl.tools@gmail.com>
Date:   Tue May 24 17:42:53 2011 -0700

    Properly handle (set reg:X (plus:X (subreg:X (reg:Y) 0) (const_int)))