From patchwork Thu May 26 23:25:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: York Sun X-Patchwork-Id: 97641 X-Patchwork-Delegate: galak@kernel.crashing.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id AF5CAB6F8B for ; Fri, 27 May 2011 09:27:08 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 825E32817F; Fri, 27 May 2011 01:26:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5DCQU+8HL5EA; Fri, 27 May 2011 01:26:47 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 441C52817C; Fri, 27 May 2011 01:26:41 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 37C0C2817C for ; Fri, 27 May 2011 01:26:40 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id awlPnFem-g35 for ; Fri, 27 May 2011 01:26:39 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from TX2EHSOBE001.bigfish.com (tx2ehsobe001.messaging.microsoft.com [65.55.88.11]) by theia.denx.de (Postfix) with ESMTPS id 059E528178 for ; Fri, 27 May 2011 01:26:27 +0200 (CEST) Received: from mail3-tx2-R.bigfish.com (10.9.14.249) by TX2EHSOBE001.bigfish.com (10.9.40.21) with Microsoft SMTP Server id 14.1.225.22; Thu, 26 May 2011 23:26:21 +0000 Received: from mail3-tx2 (localhost.localdomain [127.0.0.1]) by mail3-tx2-R.bigfish.com (Postfix) with ESMTP id CA7DCF38D04 for ; Thu, 26 May 2011 23:26:21 +0000 (UTC) X-SpamScore: 0 X-BigFish: VS0(zzzz1202hzz8275bhz2dh2a8h668h839h65h) X-Spam-TCS-SCL: 4:0 X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPVD:NLI; H:mail.freescale.net; RD:none; EFVD:NLI Received: from mail3-tx2 (localhost.localdomain [127.0.0.1]) by mail3-tx2 (MessageSwitch) id 1306452368956392_18512; Thu, 26 May 2011 23:26:08 +0000 (UTC) Received: from TX2EHSMHS026.bigfish.com (unknown [10.9.14.250]) by mail3-tx2.bigfish.com (Postfix) with ESMTP id B971615E804D for ; Thu, 26 May 2011 23:26:05 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by TX2EHSMHS026.bigfish.com (10.9.99.126) with Microsoft SMTP Server (TLS) id 14.1.225.22; Thu, 26 May 2011 23:26:03 +0000 Received: from az33smr01.freescale.net (10.64.34.199) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server id 14.1.270.2; Thu, 26 May 2011 18:26:02 -0500 Received: from localhost.localdomain (vpn-10-214-200-8.ap.freescale.net [10.214.200.8]) by az33smr01.freescale.net (8.13.1/8.13.0) with ESMTP id p4QNPv9o000699; Thu, 26 May 2011 18:26:01 -0500 (CDT) From: York Sun To: Date: Fri, 27 May 2011 07:25:49 +0800 Message-ID: <1306452353-11611-3-git-send-email-yorksun@freescale.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1306452353-11611-1-git-send-email-yorksun@freescale.com> References: <1306452353-11611-1-git-send-email-yorksun@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com Subject: [U-Boot] [PATCH 3/7] powerpc/mpc8xxx: Enable calculation for fixed DDR chips X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: york We used to have fixed parameters for soldered DDR chips. This patch enables calculation based on raw timing data, implemneted in board-specific file. Signed-off-by: York Sun --- arch/powerpc/cpu/mpc85xx/cpu.c | 4 +++- arch/powerpc/cpu/mpc8xxx/ddr/Makefile | 13 +++++++++++-- arch/powerpc/cpu/mpc8xxx/ddr/ddr.h | 5 +++++ arch/powerpc/cpu/mpc8xxx/ddr/main.c | 12 ++++++++++++ 4 files changed, 31 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f863f4a..8c2272a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -336,7 +336,9 @@ phys_size_t initdram(int board_type) } #endif -#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) +#if defined(CONFIG_SPD_EEPROM) || \ + defined(CONFIG_DDR_SPD) || \ + defined(CONFIG_DDR_RAW_TIMING) dram_size = fsl_ddr_sdram(); #else dram_size = fixed_sdram(); diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile index 4a5a785..d1b4c4b 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/Makefile +++ b/arch/powerpc/cpu/mpc8xxx/ddr/Makefile @@ -12,15 +12,24 @@ LIB = $(obj)libddr.o COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o -COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o COBJS-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o -COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o COBJS-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \ lc_common_dimm_params.o +ifdef CONFIG_DDR_SPD +SPD := y +endif +ifdef CONFIG_SPD_EEPROM +SPD := y +endif +ifdef SPD +COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o +COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o COBJS-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o +endif + SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h index 1e866fe..eb2180e 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +++ b/arch/powerpc/cpu/mpc8xxx/ddr/ddr.h @@ -14,6 +14,7 @@ #include "common_timing_params.h" +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* * Bind the main DDR setup driver's generic names * to this specific DDR technology. @@ -25,6 +26,7 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd, { return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); } +#endif /* * Data Structures @@ -80,4 +82,7 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo); extern unsigned int mclk_to_picos(unsigned int mclk); extern unsigned int get_memory_clk_period_ps(void); extern unsigned int picos_to_mclk(unsigned int picos); + +/* board specific function */ +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int dimm_number); #endif diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/main.c b/arch/powerpc/cpu/mpc8xxx/ddr/main.c index c8fa123..2b43e73 100644 --- a/arch/powerpc/cpu/mpc8xxx/ddr/main.c +++ b/arch/powerpc/cpu/mpc8xxx/ddr/main.c @@ -313,6 +313,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, switch (start_step) { case STEP_GET_SPD: +#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) /* STEP 1: Gather all DIMM SPD data */ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i); @@ -344,6 +345,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, } } +#else + case STEP_COMPUTE_DIMM_PARMS: + for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) { + for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) { + dimm_params_t *pdimm = + &(pinfo->dimm_params[i][j]); + fsl_ddr_get_dimm_params(pdimm, i); + } + } + debug("Filling dimm parameters from board specific file\n"); +#endif case STEP_COMPUTE_COMMON_PARMS: /* * STEP 3: Compute a common set of timing parameters