From patchwork Thu May 26 17:00:14 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Jander X-Patchwork-Id: 97599 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 515A4B6F7B for ; Fri, 27 May 2011 03:17:48 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 495A3280E2; Thu, 26 May 2011 19:17:46 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hgbX621RhQpA; Thu, 26 May 2011 19:17:46 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DBAD1280E9; Thu, 26 May 2011 19:17:43 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8B10F280E9 for ; Thu, 26 May 2011 19:17:41 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nu1xxhoP2Z4N for ; Thu, 26 May 2011 19:17:39 +0200 (CEST) X-Greylist: delayed 1041 seconds by postgrey-1.27 at theia; Thu, 26 May 2011 19:17:37 CEST X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from protonic.xs4all.nl (protonic.xs4all.nl [213.84.116.84]) by theia.denx.de (Postfix) with ESMTP id 0670E280E2 for ; Thu, 26 May 2011 19:17:37 +0200 (CEST) Received: from archvile.prtnl (archvile.prtnl [192.168.1.153]) by protonic.xs4all.nl (Postfix) with ESMTP id E47A829EBA; Thu, 26 May 2011 18:58:05 +0200 (CEST) From: David Jander To: u-boot@lists.denx.de Date: Thu, 26 May 2011 19:00:14 +0200 Message-Id: <1306429214-29654-1-git-send-email-david@protonic.nl> X-Mailer: git-send-email 1.7.4.1 Cc: David Jander Subject: [U-Boot] [PATCH] ARM: i.MX51: Config option to disable PLL1 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de i.MX51 PLL1 seems to have stability problems. It is advised to not use it, although it is unclear whether all boards and/or chip revisions have this problem. Using PLL2 for the core and DDR2 seems to fix the problem. No official errata yet. Signed-off-by: David Jander --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 96ebfe2..e1d6c35 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -153,7 +153,11 @@ mov r1, #0x4 str r1, [r0, #CLKCTL_CCSR] +#if defined(CONFIG_MX51_AVOID_PLL1) + setup_pll PLL1_BASE_ADDR, 216 +#else setup_pll PLL1_BASE_ADDR, 800 +#endif #if defined(CONFIG_MX51) setup_pll PLL3_BASE_ADDR, 665 @@ -165,7 +169,11 @@ str r1, [r0, #CLKCTL_CBCMR] ldr r1, =0x13239145 str r1, [r0, #CLKCTL_CBCDR] +#if defined(CONFIG_MX51_AVOID_PLL1) + setup_pll PLL2_BASE_ADDR, 800 +#else setup_pll PLL2_BASE_ADDR, 665 +#endif /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR @@ -197,7 +205,11 @@ #endif str r1, [r0, #CLKCTL_CACRR] /* Switch ARM back to PLL 1 */ +#if defined(CONFIG_MX51_AVOID_PLL1) + mov r1, #0x00000104 /* Set ARM/DDR to PLL2 */ +#else mov r1, #0 +#endif str r1, [r0, #CLKCTL_CCSR] #if defined(CONFIG_MX51) @@ -228,7 +240,11 @@ /* Use PLL 2 for UART's, get 66.5MHz from it */ ldr r1, =0xA5A2A020 str r1, [r0, #CLKCTL_CSCMR1] +#if defined(CONFIG_MX51_AVOID_PLL1) + ldr r1, =0x0104041a /* Adjust dividers for 800MHz on PLL2 */ +#else ldr r1, =0x00C30321 +#endif str r1, [r0, #CLKCTL_CSCDR1] #elif defined(CONFIG_MX53) ldr r1, [r0, #CLKCTL_CSCDR1]