From patchwork Thu Sep 27 04:48:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 975621 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 42LTyH5H5rz9s3Z for ; Thu, 27 Sep 2018 19:28:39 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 42LTyH2yVnzF377 for ; Thu, 27 Sep 2018 19:28:39 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 42LTvR2j43zF35X for ; Thu, 27 Sep 2018 19:26:10 +1000 (AEST) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w8R4moRN028785; Wed, 26 Sep 2018 23:48:58 -0500 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 27 Sep 2018 14:48:43 +1000 Message-Id: <20180927044849.28322-4-benh@kernel.crashing.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180927044849.28322-1-benh@kernel.crashing.org> References: <20180927044849.28322-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 3/9] xive: Set the fused core mode properly X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Set or clear the fused core mode bit in the XIVE inits properly. While HostBoot is supposed to do it, I prefer not depending on it doing the right thing, since we already configure that register ourselves anyway. Signed-off-by: Benjamin Herrenschmidt --- hw/xive.c | 4 ++++ include/xive.h | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 470cf5e3..f8e511c1 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1740,6 +1740,10 @@ static bool xive_config_init(struct xive *x) /* Disable pressure relief as we hijack the field in the VPs */ val &= ~PC_TCTXT_CFG_STORE_ACK; } + if (this_cpu()->is_fused_core) + val |= PC_TCTXT_CFG_FUSE_CORE_EN; + else + val &= ~PC_TCTXT_CFG_FUSE_CORE_EN; xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); diff --git a/include/xive.h b/include/xive.h index acc696a4..f4365efc 100644 --- a/include/xive.h +++ b/include/xive.h @@ -86,6 +86,7 @@ #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) +#define PC_TCTXT_CFG_FUSE_CORE_EN PPC_BIT(4) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15)