[3/9] xive: Set the fused core mode properly

Message ID 20180927044849.28322-4-benh@kernel.crashing.org
State Under Review
Headers show
Series
  • Initial "big cores" support for POWER9
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Commit Message

Benjamin Herrenschmidt Sept. 27, 2018, 4:48 a.m.
Set or clear the fused core mode bit in the XIVE inits
properly. While HostBoot is supposed to do it, I prefer
not depending on it doing the right thing, since we already
configure that register ourselves anyway.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 hw/xive.c      | 4 ++++
 include/xive.h | 1 +
 2 files changed, 5 insertions(+)

Patch

diff --git a/hw/xive.c b/hw/xive.c
index 470cf5e3..f8e511c1 100644
--- a/hw/xive.c
+++ b/hw/xive.c
@@ -1740,6 +1740,10 @@  static bool xive_config_init(struct xive *x)
 		/* Disable pressure relief as we hijack the field in the VPs */
 		val &= ~PC_TCTXT_CFG_STORE_ACK;
 	}
+	if (this_cpu()->is_fused_core)
+		val |= PC_TCTXT_CFG_FUSE_CORE_EN;
+	else
+		val &= ~PC_TCTXT_CFG_FUSE_CORE_EN;
 	xive_regw(x, PC_TCTXT_CFG, val);
 	xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val);
 
diff --git a/include/xive.h b/include/xive.h
index acc696a4..f4365efc 100644
--- a/include/xive.h
+++ b/include/xive.h
@@ -86,6 +86,7 @@ 
 #define  PC_TCTXT_CFG_TARGET_EN		PPC_BIT(1)
 #define  PC_TCTXT_CFG_LGS_EN		PPC_BIT(2)
 #define  PC_TCTXT_CFG_STORE_ACK		PPC_BIT(3)
+#define  PC_TCTXT_CFG_FUSE_CORE_EN	PPC_BIT(4)
 #define  PC_TCTXT_CFG_HARD_CHIPID_BLK	PPC_BIT(8)
 #define  PC_TCTXT_CHIPID_OVERRIDE	PPC_BIT(9)
 #define  PC_TCTXT_CHIPID		PPC_BITMASK(12,15)