Patchwork [U-Boot] SMDKV310: CPU fequency and mmc_pre_ratio modified

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Submitter Chander Kashyap
Date May 26, 2011, 11:10 a.m.
Message ID <1306408234-21309-1-git-send-email-chander.kashyap@linaro.org>
Download mbox | patch
Permalink /patch/97561/
State Accepted
Commit cb56c0237dfd2d3ef19835108626a1aebaca894d
Delegated to: Albert ARIBAUD
Headers show

Comments

Chander Kashyap - May 26, 2011, 11:10 a.m.
Modifies CPU Frequency to 1GHz and removes hard coding of mmc_pre_ratio for
MMC Channel2 in FSYS2 register.

Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
---
 board/samsung/smdkv310/lowlevel_init.S |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
Minkyu Kang - June 1, 2011, 2:46 a.m.
On 26 May 2011 20:10, Chander Kashyap <chander.kashyap@linaro.org> wrote:
> Modifies CPU Frequency to 1GHz and removes hard coding of mmc_pre_ratio for
> MMC Channel2 in FSYS2 register.
>
> Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
> ---
>  board/samsung/smdkv310/lowlevel_init.S |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>

Acked-by: Minkyu Kang <mk7.kang@samsung.com>


Dear Albert ARIBAUD,

This patch is for bugfix.
Please apply it to arm tree directly.

Thanks
Minkyu Kang
Albert ARIBAUD - June 1, 2011, 5:44 p.m.
Hi Chander,

Le 26/05/2011 13:10, Chander Kashyap a écrit :
> Modifies CPU Frequency to 1GHz and removes hard coding of mmc_pre_ratio for
> MMC Channel2 in FSYS2 register.
>
> Signed-off-by: Chander Kashyap<chander.kashyap@linaro.org>
> ---
>   board/samsung/smdkv310/lowlevel_init.S |    4 ++--
>   1 files changed, 2 insertions(+), 2 deletions(-)

Upon Minkyu's request: applied to u-boot-arm/master, thanks!

Amicalement,

Patch

diff --git a/board/samsung/smdkv310/lowlevel_init.S b/board/samsung/smdkv310/lowlevel_init.S
index 359cff4..04f6579 100644
--- a/board/samsung/smdkv310/lowlevel_init.S
+++ b/board/samsung/smdkv310/lowlevel_init.S
@@ -170,7 +170,7 @@  system_clock_init:
 	 * COREM1_RATIO[8]	0x7
 	 * COREM0_RATIO[4]	0x3
 	 */
-	ldr	r1, =0x01133730
+	ldr	r1, =0x0133730
 	ldr	r2, =0x14500			@CLK_DIV_CPU0_OFFSET
 	str	r1, [r0, r2]
 
@@ -245,7 +245,7 @@  system_clock_init:
 	str	r1, [r0, r2]
 
 	/* MMC[2:3] */
-	ldr	r1, =0x000f020f			/* 800(MPLL) / (15 + 1) */
+	ldr	r1, =0x000f000f			/* 800(MPLL) / (15 + 1) */
 	ldr	r2, =0x0C548			@ CLK_DIV_FSYS2
 	str	r1, [r0, r2]