[V2] clk: tegra: Return the exact clock rate from clk_round_rate
diff mbox series

Message ID 20180925214940.15188-1-decatf@gmail.com
State Deferred
Headers show
Series
  • [V2] clk: tegra: Return the exact clock rate from clk_round_rate
Related show

Commit Message

Robert Yang Sept. 25, 2018, 9:49 p.m. UTC
The current behavior is that clk_round_rate would return the same clock
rate passed to it for valid PLL configurations. This change will return
the exact rate the PLL will provide in accordance with clk API.

Signed-off-by: Robert Yang <decatf@gmail.com>
---
Changes in V2:
 - Move input divider (m == 0) check into the cfg constraints check
   condition. Forgo adding WARN_ON and avoid using 0 input divider
   all together.

 drivers/clk/tegra/clk-pll.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

Comments

Stephen Boyd Oct. 16, 2018, 10:47 p.m. UTC | #1
Quoting Robert Yang (2018-09-25 14:49:40)
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
> 
> Signed-off-by: Robert Yang <decatf@gmail.com>
> ---

I'm waiting for someone from Nvidia/Tegra background to review this
change.
Dmitry Osipenko Nov. 27, 2018, 7:40 p.m. UTC | #2
On 17.10.2018 1:47, Stephen Boyd wrote:
> Quoting Robert Yang (2018-09-25 14:49:40)
>> The current behavior is that clk_round_rate would return the same clock
>> rate passed to it for valid PLL configurations. This change will return
>> the exact rate the PLL will provide in accordance with clk API.
>>
>> Signed-off-by: Robert Yang <decatf@gmail.com>
>> ---
> 
> I'm waiting for someone from Nvidia/Tegra background to review this
> change.
> 

Apparently Peter is taking a pause. I think Thierry's ACK to V1 should be still valid here.

Also, if this helps:

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Thierry Reding Nov. 28, 2018, 9:16 a.m. UTC | #3
On Tue, Sep 25, 2018 at 05:49:40PM -0400, Robert Yang wrote:
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
> 
> Signed-off-by: Robert Yang <decatf@gmail.com>
> ---
> Changes in V2:
>  - Move input divider (m == 0) check into the cfg constraints check
>    condition. Forgo adding WARN_ON and avoid using 0 input divider
>    all together.
> 
>  drivers/clk/tegra/clk-pll.c | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)

Acked-by: Thierry Reding <treding@nvidia.com>
Stephen Boyd Dec. 10, 2018, 7:11 p.m. UTC | #4
Quoting Robert Yang (2018-09-25 14:49:40)
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
> 
> Signed-off-by: Robert Yang <decatf@gmail.com>
> ---

Applied to clk-next

Patch
diff mbox series

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 17a058c3bbc1..2a800a9c56e6 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -589,12 +589,13 @@  static int _calc_rate(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,
 	cfg->n = cfg->output_rate / cfreq;
 	cfg->cpcon = OUT_OF_TABLE_CPCON;
 
-	if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||
-	    (1 << p_div) > divp_max(pll)
-	    || cfg->output_rate > pll->params->vco_max) {
+	if (cfg->m == 0 || cfg->m > divm_max(pll) ||
+	    cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) ||
+	    cfg->output_rate > pll->params->vco_max) {
 		return -EINVAL;
 	}
 
+	cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m);
 	cfg->output_rate >>= p_div;
 
 	if (pll->params->pdiv_tohw) {