Patchwork PATCH: PR target/49142: Invalid 8bit register operand

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Submitter H.J. Lu
Date May 25, 2011, 4:20 p.m.
Message ID <BANLkTikeiTJ7pmwoiFTOtmNCuxOuC1f1CQ@mail.gmail.com>
Download mbox | patch
Permalink /patch/97379/
State New
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Comments

H.J. Lu - May 25, 2011, 4:20 p.m.
On Wed, May 25, 2011 at 8:30 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Wed, May 25, 2011 at 4:42 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
>> On Wed, May 25, 2011 at 7:00 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
>>> On Tue, May 24, 2011 at 5:54 PM, H.J. Lu <hongjiu.lu@intel.com> wrote:
>>>> Hi,
>>>>
>>>> We are working on a new optimization, which turns off TARGET_MOVX.
>>>> GCC generates:
>>>>
>>>> movb %ah, %dil
>>>>
>>>> But %ah can only be used with %[abcd][hl].  This patch adds QIreg_operand
>>>> and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64.  OK for trunk
>>>> if there is no regression? and Replace
>       q_regs_operand with QIreg_operand.
>       (
>>>
>>> If this is the case, then please change "q_regs_operand" predicate to
>>> accept just QI_REG_P registers.
>>>
>>
>> I thought about it.  It is a problem only with %[abcd]h.  I am not sure if
>> changing q_regs_operand to  accept just QI_REG_P registers will negatively
>> impact
>
> I see. The patch is OK then, but for consistency, please change the
> predicate of *movqi_extv_1*movqi_extzv_2 as well. Oh, and the
> "register_operand" check in "type" calculation can be removed.
>
> Thanks,
> Uros.
>

This is what I checked in.

Thanks.
Uros Bizjak - May 25, 2011, 7:11 p.m.
On Wed, May 25, 2011 at 6:20 PM, H.J. Lu <hjl.tools@gmail.com> wrote:

>>>>> We are working on a new optimization, which turns off TARGET_MOVX.
>>>>> GCC generates:
>>>>>
>>>>> movb %ah, %dil
>>>>>
>>>>> But %ah can only be used with %[abcd][hl].  This patch adds QIreg_operand
>>>>> and uses it in *movqi_extv_1_rex64/*movqi_extzv_2_rex64.  OK for trunk
>>>>> if there is no regression? and Replace
>>       q_regs_operand with QIreg_operand.
>>       (
>>>>
>>>> If this is the case, then please change "q_regs_operand" predicate to
>>>> accept just QI_REG_P registers.
>>>>
>>>
>>> I thought about it.  It is a problem only with %[abcd]h.  I am not sure if
>>> changing q_regs_operand to  accept just QI_REG_P registers will negatively
>>> impact
>>
>> I see. The patch is OK then, but for consistency, please change the
>> predicate of *movqi_extv_1*movqi_extzv_2 as well. Oh, and the
>> "register_operand" check in "type" calculation can be removed.
>>
>> Thanks,
>> Uros.
>>
>
> This is what I checked in.
>
> Thanks.
>
> --
> H.J.
> ---
> 2011-05-25  H.J. Lu  <hongjiu.lu@intel.com>
>
>        PR target/49142
>        * config/i386/i386.md (*movqi_extv_1_rex64): Remove
>        "register_operand" check and replace q_regs_operand with
>        QIreg_operand in "type" calculation.
>        (*movqi_extv_1): Likewise.
>        (*movqi_extzv_2_rex64): Likewise.
>        (*movqi_extzv_2): Likewise.

Er, I didn't mean to remove register_operand check from 32bit
patterns... there, operand 0 can also be memory operand due to
"nonimmediate_operand" constraint.

Uros.

Patch

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 49f1ee7..3b59024 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -2487,10 +2487,9 @@ 
     }
 }
   [(set (attr "type")
-     (if_then_else (and (match_operand:QI 0 "register_operand" "")
-			(ior (not (match_operand:QI 0 "q_regs_operand" ""))
-			     (ne (symbol_ref "TARGET_MOVX")
-				 (const_int 0))))
+     (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+			(ne (symbol_ref "TARGET_MOVX")
+			    (const_int 0)))
 	(const_string "imovx")
 	(const_string "imov")))
    (set (attr "mode")
@@ -2514,10 +2513,9 @@ 
     }
 }
   [(set (attr "type")
-     (if_then_else (and (match_operand:QI 0 "register_operand" "")
-			(ior (not (match_operand:QI 0 "q_regs_operand" ""))
-			     (ne (symbol_ref "TARGET_MOVX")
-				 (const_int 0))))
+     (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+			(ne (symbol_ref "TARGET_MOVX")
+			    (const_int 0)))
 	(const_string "imovx")
 	(const_string "imov")))
    (set (attr "mode")
@@ -2552,7 +2550,7 @@ 
     }
 }
   [(set (attr "type")
-     (if_then_else (ior (not (match_operand:QI 0 "q_regs_operand" ""))
+     (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
 			(ne (symbol_ref "TARGET_MOVX")
 			    (const_int 0)))
 	(const_string "imovx")
@@ -2579,10 +2577,9 @@ 
     }
 }
   [(set (attr "type")
-     (if_then_else (and (match_operand:QI 0 "register_operand" "")
-			(ior (not (match_operand:QI 0 "q_regs_operand" ""))
-			     (ne (symbol_ref "TARGET_MOVX")
-				 (const_int 0))))
+     (if_then_else (ior (not (match_operand:QI 0 "QIreg_operand" ""))
+			(ne (symbol_ref "TARGET_MOVX")
+			    (const_int 0)))
 	(const_string "imovx")
 	(const_string "imov")))
    (set (attr "mode")
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 8a89f70..1471f5a 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -82,6 +82,10 @@ 
   (and (match_code "reg")
        (match_test "REGNO (op) == FLAGS_REG")))

+;; Return true if op is one of QImode registers: %[abcd][hl].
+(define_predicate "QIreg_operand"
+  (match_test "QI_REG_P (op)"))
+
 ;; Return true if op is a QImode register operand other than
 ;; %[abcd][hl].
 (define_predicate "ext_QIreg_operand"