Patchwork [00/26] q35 chipset support for native pci express support

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Submitter Jan Kiszka
Date May 25, 2011, 7:15 a.m.
Message ID <4DDCACAB.1090208@web.de>
Download mbox | patch
Permalink /patch/97351/
State New
Headers show

Comments

Jan Kiszka - May 25, 2011, 7:15 a.m.
On 2011-05-17 09:15, Jan Kiszka wrote:
> On 2011-05-16 23:55, Adnan Khaleel wrote:
>> I finally got this work after I realised that the AHCI driver was not being loaded in my disk image and that ACHI was not being enabled in the Seabios .config file.
>> This is really good work Yamahata, thanks.
>>
>>
>> As far as I can tell, everything works like the stock Qemu 0.14 except networking. The guest OS sees the network device and initialises it but I think the Qemu DHCP server/firewall never gets back, since the network device doesn't even get a 10.0.2.15 ip address during bootup and the guest dhcp client never gets an ip address, 
>>
>>
>> eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
>> eth0   Starting DHCP4 client. . . . . . . .
>> eth0   DHCP4 continues in background 
>> eth0   device: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03)
>> eth0   DHCP4 client (dhcpcd) is running
>> eth0   . . . but is still waiting for data
>> eth0   interface could not be set up until now
>>
>>
>> So doing an ifconfig later on just shows
>>
>>
>> eth0   Link encap:Ethernet  HWaddr 52:54:00:12:34:56
>>          UP BROADCAST MULTICAST  MTU:1500  Metric:1
>>          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>>          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>>          collisions:0 txqueuelen:1000
>>          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
>>
>>
>>
>> lo      Link encap:Local loopback  
>>          inet addr:127.0.0.1  Mask:255.0.0.0
>>          inet6 addr: ::1/128 Scope:Host
>>          UP LOOPBACK RUNING  MTU:16436  Metric:1
>>          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
>>          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
>>          collisions:0 txqueuelen:1000
>>          RX bytes:0 (0.0 b)   TX bytes:0 (0.0 b)
>>
>>
>> I'm going to start a separate thread to see what the possible cause might be and what might be the best way to debug this. Do you have any idea if this q35 chipset going to be committed to Qemu upstream?
> 
> I've recently hacked a bit on q35, rebased it over current master, found
> and fixed a few bugs to allow booting of WinXP and Win7, and
> particularly added kvm support to improve testability significantly. You
> can find my current work at
> 
> git://git.kiszka.org/qemu.git q35-test
> git://git.kiszka.org/seabios.git q35-test
> 
> There are some issues remaining, e.g. usb appeared broken to me. Now I
> just tested your scenario (e1000+usernet) with a Win7 guest, and I do
> not get an IP either. There is no traffic on the vlan (I attached a dump
> device to verify). Looking closer, it seems PCI bar mapping is failing,
> at least partially, see 'info pci'. I hope it's not yet another ACPI
> issue. Fixing the polarity bug already forced me to dig way too deep
> into this horrible domain.

FWIW, patch below fixes UHCI here. I suspect more bugs in this area as
accessing the chip_config registers appears to rely on the host being
little endian (direct memcpy).

In contrast, the PCI mapping issue turned out to be a read herring. The
unmapped regions were actually ROM BARs which are usually unmapped. And
the network issues were related to an outdated DSDT. Somehow rebuilding
Seabios did not always properly regenerate them, so my polarity fixes
were not inluded. Haven't looked into details, but deleting out/ and
src/*.hex resolved that.

I'll have to put this topic aside for now as it looks like we don't
depend on it for PCIe pass-through. Still, it's a cool thing, and I
would be happy to find it upstream soon!

Jan

------8<-------

From: Jan Kiszka <jan.kiszka@siemens.com>
Subject: [PATCH] q35: Fix irr initialization for slots 25..31

This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 hw/q35.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)
Isaku Yamahata - May 26, 2011, 9 a.m.
On Wed, May 25, 2011 at 09:15:55AM +0200, Jan Kiszka wrote:
> FWIW, patch below fixes UHCI here. I suspect more bugs in this area as
> accessing the chip_config registers appears to rely on the host being
> little endian (direct memcpy).
> 
> In contrast, the PCI mapping issue turned out to be a read herring. The
> unmapped regions were actually ROM BARs which are usually unmapped. And
> the network issues were related to an outdated DSDT. Somehow rebuilding
> Seabios did not always properly regenerate them, so my polarity fixes
> were not inluded. Haven't looked into details, but deleting out/ and
> src/*.hex resolved that.

Good catch. I queued it in my repo.


> 
> I'll have to put this topic aside for now as it looks like we don't
> depend on it for PCIe pass-through. Still, it's a cool thing, and I
> would be happy to find it upstream soon!
> 
> Jan
> 
> ------8<-------
> 
> From: Jan Kiszka <jan.kiszka@siemens.com>
> Subject: [PATCH] q35: Fix irr initialization for slots 25..31
> 
> This was totally off: The CC registers are 16 bit (stored as little
> endian), their offsets run in reverse order, and D26IR as well as D25IR
> have 4 bytes offset to their successors.
> 
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> ---
>  hw/q35.c |   10 +++++++---
>  1 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/q35.c b/hw/q35.c
> index a06ea7d..0ab8532 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -424,14 +424,18 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
>  static void ich9_cc_update(ICH9_LPCState *lpc)
>  {
>      int slot;
> -    int reg_offset;
> +    int reg;
>      int intx;
>  
>      /* D{25 - 31}IR, but D30IR is read only to 0. */
> -    for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> +    for (slot = 31, reg = ICH9_CC_D31IR; slot >= 25; slot--, reg += 2) {
>          if (slot != 30) {
>              ich9_cc_update_ir(lpc->irr[slot],
> -                              lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> +                              lpc->chip_config[reg] |
> +                              (uint32_t)lpc->chip_config[reg + 1] << 8);
> +        }
> +        if (slot <= 27) {
> +            reg += 2;
>          }
>      }
>  
> -- 
> 1.7.1
>

Patch

diff --git a/hw/q35.c b/hw/q35.c
index a06ea7d..0ab8532 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -424,14 +424,18 @@  static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
 static void ich9_cc_update(ICH9_LPCState *lpc)
 {
     int slot;
-    int reg_offset;
+    int reg;
     int intx;
 
     /* D{25 - 31}IR, but D30IR is read only to 0. */
-    for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
+    for (slot = 31, reg = ICH9_CC_D31IR; slot >= 25; slot--, reg += 2) {
         if (slot != 30) {
             ich9_cc_update_ir(lpc->irr[slot],
-                              lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
+                              lpc->chip_config[reg] |
+                              (uint32_t)lpc->chip_config[reg + 1] << 8);
+        }
+        if (slot <= 27) {
+            reg += 2;
         }
     }