| Message ID | b9bb7396-b2e5-6df5-cb0f-6cee29860491@gmail.com |
|---|---|
| State | Accepted, archived |
| Delegated to: | David Miller |
| Headers | show |
| Series | [net-next,1/2] r8169: simplify RTL8169 PHY initialization | expand |
From: Heiner Kallweit <hkallweit1@gmail.com> Date: Wed, 19 Sep 2018 22:02:11 +0200 > Setting register 0x82 to value 01 is done a few lines before for all > chip versions <= 06 anyway. And setting PHY register 0x0b to value 00 > is done at the end of rtl8169s_hw_phy_config() already. So we can > remove this. > > Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Applied.
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c index a27bf5807..e2713867c 100644 --- a/drivers/net/ethernet/realtek/r8169.c +++ b/drivers/net/ethernet/realtek/r8169.c @@ -4053,15 +4053,6 @@ static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) RTL_W8(tp, 0x82, 0x01); } - if (tp->mac_version == RTL_GIGA_MAC_VER_02) { - netif_dbg(tp, drv, dev, - "Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); - RTL_W8(tp, 0x82, 0x01); - netif_dbg(tp, drv, dev, - "Set PHY Reg 0x0bh = 0x00h\n"); - rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 - } - /* We may have called phy_speed_down before */ phy_speed_up(dev->phydev);
Setting register 0x82 to value 01 is done a few lines before for all chip versions <= 06 anyway. And setting PHY register 0x0b to value 00 is done at the end of rtl8169s_hw_phy_config() already. So we can remove this. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> --- drivers/net/ethernet/realtek/r8169.c | 9 --------- 1 file changed, 9 deletions(-)