| Message ID | 207741bf9c994a869f574a93d4fb4152d4e169c9.1537163779.git.christophe.leroy@c-s.fr (mailing list archive) |
|---|---|
| State | Not Applicable |
| Headers | show |
| Series | [v3,1/3] watchdog: mpc8xxx: use dev_xxxx() instead of pr_xxxx() | expand |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | next/apply_patch Successfully applied |
| snowpatch_ozlabs/checkpatch | success | Test checkpatch on branch next |
On Mon, Sep 17, 2018 at 06:22:50AM +0000, Christophe Leroy wrote: > mpc8xxx watchdog driver supports the following platforms: > - mpc8xx > - mpc83xx > - mpc86xx > > Those three platforms have a 32 bits register which provides the > reason of the last boot, including whether it was caused by the > watchdog. > > mpc8xx: Register RSR, bit SWRS (bit 3) > mpc83xx: Register RSR, bit SWRS (bit 28) > mpc86xx: Register RSTRSCR, bit WDT_RR (bit 11) > > This patch maps the register as defined in the device tree and updates > wdt.bootstatus based on the value of the watchdog related bit. Then > the information can be retrieved via the WDIOC_GETBOOTSTATUS ioctl. > > Hereunder is an example of devicetree for mpc8xx, > the Reset Status Register being at offset 0x288: > > WDT: watchdog@0 { > compatible = "fsl,mpc823-wdt"; > reg = <0x0 0x10 0x288 0x4>; > }; > > On the mpc83xx, RSR is at offset 0x910 > On the mpc86xx, RSTRSCR is at offset 0xe0094 > > Suggested-by: Radu Rendec <radu.rendec@gmail.com> > Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> # On mpc885 > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> > --- I am ok with the patch, though I would really appreciate change logs in the future. Consider this an informal Reviewed-by:. Waiting for DT review before final approval. Guenter > drivers/watchdog/mpc8xxx_wdt.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c > index 1dcf5f10cdd9..069072e6747d 100644 > --- a/drivers/watchdog/mpc8xxx_wdt.c > +++ b/drivers/watchdog/mpc8xxx_wdt.c > @@ -47,6 +47,7 @@ struct mpc8xxx_wdt { > struct mpc8xxx_wdt_type { > int prescaler; > bool hw_enabled; > + u32 rsr_mask; > }; > > struct mpc8xxx_wdt_ddata { > @@ -159,6 +160,24 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev) > return -ENODEV; > } > > + res = platform_get_resource(ofdev, IORESOURCE_MEM, 1); > + if (res) { > + bool status; > + u32 __iomem *rsr = ioremap(res->start, resource_size(res)); > + > + if (!rsr) > + return -ENOMEM; > + > + status = in_be32(rsr) & wdt_type->rsr_mask; > + ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0; > + /* clear reset status bits related to watchdog timer */ > + out_be32(rsr, wdt_type->rsr_mask); > + iounmap(rsr); > + > + dev_info(dev, "Last boot was %scaused by watchdog\n", > + status ? "" : "not "); > + } > + > spin_lock_init(&ddata->lock); > > ddata->wdd.info = &mpc8xxx_wdt_info, > @@ -216,6 +235,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .compatible = "mpc83xx_wdt", > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > + .rsr_mask = BIT(3), /* RSR Bit SWRS */ > }, > }, > { > @@ -223,6 +243,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > .hw_enabled = true, > + .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */ > }, > }, > { > @@ -230,6 +251,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x800, > .hw_enabled = true, > + .rsr_mask = BIT(28), /* RSR Bit SWRS */ > }, > }, > {}, > -- > 2.13.3 >
On Mon, Sep 17, 2018 at 06:22:50AM +0000, Christophe Leroy wrote: > mpc8xxx watchdog driver supports the following platforms: > - mpc8xx > - mpc83xx > - mpc86xx > > Those three platforms have a 32 bits register which provides the > reason of the last boot, including whether it was caused by the > watchdog. > > mpc8xx: Register RSR, bit SWRS (bit 3) > mpc83xx: Register RSR, bit SWRS (bit 28) > mpc86xx: Register RSTRSCR, bit WDT_RR (bit 11) > > This patch maps the register as defined in the device tree and updates > wdt.bootstatus based on the value of the watchdog related bit. Then > the information can be retrieved via the WDIOC_GETBOOTSTATUS ioctl. > > Hereunder is an example of devicetree for mpc8xx, > the Reset Status Register being at offset 0x288: > > WDT: watchdog@0 { > compatible = "fsl,mpc823-wdt"; > reg = <0x0 0x10 0x288 0x4>; > }; > > On the mpc83xx, RSR is at offset 0x910 > On the mpc86xx, RSTRSCR is at offset 0xe0094 > > Suggested-by: Radu Rendec <radu.rendec@gmail.com> > Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> # On mpc885 > Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Reviewed-by: Guenter Roeck <linux@roeck-us.net> > --- > drivers/watchdog/mpc8xxx_wdt.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c > index 1dcf5f10cdd9..069072e6747d 100644 > --- a/drivers/watchdog/mpc8xxx_wdt.c > +++ b/drivers/watchdog/mpc8xxx_wdt.c > @@ -47,6 +47,7 @@ struct mpc8xxx_wdt { > struct mpc8xxx_wdt_type { > int prescaler; > bool hw_enabled; > + u32 rsr_mask; > }; > > struct mpc8xxx_wdt_ddata { > @@ -159,6 +160,24 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev) > return -ENODEV; > } > > + res = platform_get_resource(ofdev, IORESOURCE_MEM, 1); > + if (res) { > + bool status; > + u32 __iomem *rsr = ioremap(res->start, resource_size(res)); > + > + if (!rsr) > + return -ENOMEM; > + > + status = in_be32(rsr) & wdt_type->rsr_mask; > + ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0; > + /* clear reset status bits related to watchdog timer */ > + out_be32(rsr, wdt_type->rsr_mask); > + iounmap(rsr); > + > + dev_info(dev, "Last boot was %scaused by watchdog\n", > + status ? "" : "not "); > + } > + > spin_lock_init(&ddata->lock); > > ddata->wdd.info = &mpc8xxx_wdt_info, > @@ -216,6 +235,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .compatible = "mpc83xx_wdt", > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > + .rsr_mask = BIT(3), /* RSR Bit SWRS */ > }, > }, > { > @@ -223,6 +243,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x10000, > .hw_enabled = true, > + .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */ > }, > }, > { > @@ -230,6 +251,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { > .data = &(struct mpc8xxx_wdt_type) { > .prescaler = 0x800, > .hw_enabled = true, > + .rsr_mask = BIT(28), /* RSR Bit SWRS */ > }, > }, > {},
diff --git a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c index 1dcf5f10cdd9..069072e6747d 100644 --- a/drivers/watchdog/mpc8xxx_wdt.c +++ b/drivers/watchdog/mpc8xxx_wdt.c @@ -47,6 +47,7 @@ struct mpc8xxx_wdt { struct mpc8xxx_wdt_type { int prescaler; bool hw_enabled; + u32 rsr_mask; }; struct mpc8xxx_wdt_ddata { @@ -159,6 +160,24 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev) return -ENODEV; } + res = platform_get_resource(ofdev, IORESOURCE_MEM, 1); + if (res) { + bool status; + u32 __iomem *rsr = ioremap(res->start, resource_size(res)); + + if (!rsr) + return -ENOMEM; + + status = in_be32(rsr) & wdt_type->rsr_mask; + ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0; + /* clear reset status bits related to watchdog timer */ + out_be32(rsr, wdt_type->rsr_mask); + iounmap(rsr); + + dev_info(dev, "Last boot was %scaused by watchdog\n", + status ? "" : "not "); + } + spin_lock_init(&ddata->lock); ddata->wdd.info = &mpc8xxx_wdt_info, @@ -216,6 +235,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { .compatible = "mpc83xx_wdt", .data = &(struct mpc8xxx_wdt_type) { .prescaler = 0x10000, + .rsr_mask = BIT(3), /* RSR Bit SWRS */ }, }, { @@ -223,6 +243,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { .data = &(struct mpc8xxx_wdt_type) { .prescaler = 0x10000, .hw_enabled = true, + .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */ }, }, { @@ -230,6 +251,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { .data = &(struct mpc8xxx_wdt_type) { .prescaler = 0x800, .hw_enabled = true, + .rsr_mask = BIT(28), /* RSR Bit SWRS */ }, }, {},
mpc8xxx watchdog driver supports the following platforms: - mpc8xx - mpc83xx - mpc86xx Those three platforms have a 32 bits register which provides the reason of the last boot, including whether it was caused by the watchdog. mpc8xx: Register RSR, bit SWRS (bit 3) mpc83xx: Register RSR, bit SWRS (bit 28) mpc86xx: Register RSTRSCR, bit WDT_RR (bit 11) This patch maps the register as defined in the device tree and updates wdt.bootstatus based on the value of the watchdog related bit. Then the information can be retrieved via the WDIOC_GETBOOTSTATUS ioctl. Hereunder is an example of devicetree for mpc8xx, the Reset Status Register being at offset 0x288: WDT: watchdog@0 { compatible = "fsl,mpc823-wdt"; reg = <0x0 0x10 0x288 0x4>; }; On the mpc83xx, RSR is at offset 0x910 On the mpc86xx, RSTRSCR is at offset 0xe0094 Suggested-by: Radu Rendec <radu.rendec@gmail.com> Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> # On mpc885 Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> --- drivers/watchdog/mpc8xxx_wdt.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)