From patchwork Mon May 23 20:28:27 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 97036 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [140.186.70.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 973B3B6FBB for ; Tue, 24 May 2011 06:29:42 +1000 (EST) Received: from localhost ([::1]:50236 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkx-0004zN-Pb for incoming@patchwork.ozlabs.org; Mon, 23 May 2011 16:29:39 -0400 Received: from eggs.gnu.org ([140.186.70.92]:42677) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkR-0004s9-Sp for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QObkR-0008Jn-26 for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:07 -0400 Received: from mail-yx0-f173.google.com ([209.85.213.173]:41513) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QObkQ-0008JS-Vw for qemu-devel@nongnu.org; Mon, 23 May 2011 16:29:07 -0400 Received: by mail-yx0-f173.google.com with SMTP id 8so2718000yxk.4 for ; Mon, 23 May 2011 13:29:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:sender:from:to:subject:date:message-id:x-mailer :in-reply-to:references; bh=B0/KU8/3+WbUNjnygp+dE+bPEVl5FjElQ0wlicQQ+II=; b=XXxdPyAo+0X5MDwWg1C5vfUkH4qpdezVs+D+XmuShEP3Of94nmQPcvA+wAo5vLQSQN y3DLr54ssZahUabPLMbZu1fvt9kj183PdOLHknrEC/rkRWPixb4fO+8Gzdn650nU6tPd fNyb37+gONcrc2doEg7HvphHDFRVj/M00/Oew= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:message-id:x-mailer:in-reply-to :references; b=g2uVmHj+W6Lfk4rawYzk0ogkYf+a3nnkjDRgGmPZyeDFAp560jOo1LJcwkL9esqXZu o2SL34DU4gKgDJtbXFY/3bnC/3YpsGq9OflFUhyckmIjX472asAxceGzVcF0MzUvHbPw pBBQteiqiCDHXDpe6dP2u07aAc7HhYww8yLNk= Received: by 10.101.171.16 with SMTP id y16mr4625791ano.82.1306182546741; Mon, 23 May 2011 13:29:06 -0700 (PDT) Received: from localhost.localdomain (c-71-227-161-214.hsd1.wa.comcast.net [71.227.161.214]) by mx.google.com with ESMTPS id e9sm5033668ann.24.2011.05.23.13.29.05 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 23 May 2011 13:29:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 23 May 2011 13:28:27 -0700 Message-Id: <1306182526-12081-8-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.4.4 In-Reply-To: <1306182526-12081-1-git-send-email-rth@twiddle.net> References: <1306182526-12081-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 2) X-Received-From: 209.85.213.173 Subject: [Qemu-devel] [PATCH 07/26] target-alpha: Cleanup MMU modes. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Don't bother including executive and supervisor modes. Signed-off-by: Richard Henderson --- target-alpha/cpu.h | 37 ++++++++++++++++++++++++++++--------- target-alpha/translate.c | 7 ++++--- 2 files changed, 32 insertions(+), 12 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 0daa556..6b9deb3 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -317,9 +317,34 @@ enum { IPR_LAST, }; -typedef struct CPUAlphaState CPUAlphaState; +/* MMU modes definitions */ + +/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user. + The Unix PALcode only exposes the kernel and user modes; presumably + executive and supervisor are used by VMS. + + PALcode itself uses physical mode for code and kernel mode for data; + there are PALmode instructions that can access data via physical mode + or via an os-installed "alternate mode", which is one of the 4 above. + + QEMU does not currently properly distinguish between code/data when + looking up addresses. To avoid having to address this issue, our + emulated PALcode will cheat and use the KSEG mapping for its code+data + rather than physical addresses. + + Moreover, we're only emulating Unix PALcode, and not attempting VMS. + + All of which allows us to drop all but kernel and user modes. + Elide the unused MMU modes to save space. */ -#define NB_MMU_MODES 4 +#define NB_MMU_MODES 2 + +#define MMU_MODE0_SUFFIX _kernel +#define MMU_MODE1_SUFFIX _user +#define MMU_KERNEL_IDX 0 +#define MMU_USER_IDX 1 + +typedef struct CPUAlphaState CPUAlphaState; struct CPUAlphaState { uint64_t ir[31]; @@ -370,15 +395,9 @@ struct CPUAlphaState { #define cpu_gen_code cpu_alpha_gen_code #define cpu_signal_handler cpu_alpha_signal_handler -/* MMU modes definitions */ -#define MMU_MODE0_SUFFIX _kernel -#define MMU_MODE1_SUFFIX _executive -#define MMU_MODE2_SUFFIX _supervisor -#define MMU_MODE3_SUFFIX _user -#define MMU_USER_IDX 3 static inline int cpu_mmu_index (CPUState *env) { - return (env->ps >> 3) & 3; + return (env->ps >> 3) & 1; } #include "cpu-all.h" diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 851a045..2c0b9c2 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -1522,8 +1522,9 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) #ifndef CONFIG_USER_ONLY if (palcode < 0x40) { /* Privileged PAL code */ - if (ctx->mem_idx & 1) + if (ctx->mem_idx != MMU_KERNEL_IDX) { goto invalid_opc; + } ret = gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x3F) << 6), 0); } #endif @@ -2651,11 +2652,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) goto invalid_opc; case 0xA: /* Longword virtual access with protection check (hw_ldl/w) */ - tcg_gen_qemu_ld32s(cpu_ir[ra], addr, 0); + tcg_gen_qemu_ld32s(cpu_ir[ra], addr, MMU_KERNEL_IDX); break; case 0xB: /* Quadword virtual access with protection check (hw_ldq/w) */ - tcg_gen_qemu_ld64(cpu_ir[ra], addr, 0); + tcg_gen_qemu_ld64(cpu_ir[ra], addr, MMU_KERNEL_IDX); break; case 0xC: /* Longword virtual access with alt access mode (hw_ldl/a)*/