From patchwork Sun Sep 9 11:41:39 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaibhav Jain X-Patchwork-Id: 967744 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 427TnL5vVhz9s2P for ; Sun, 9 Sep 2018 21:42:46 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 427TnL4dBzzF3Cs for ; Sun, 9 Sep 2018 21:42:46 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=vaibhav@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 427Tmn3QN4zF3D3 for ; Sun, 9 Sep 2018 21:42:17 +1000 (AEST) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w89BdMvd062378 for ; Sun, 9 Sep 2018 07:42:15 -0400 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0b-001b2d01.pphosted.com with ESMTP id 2mcuebk90g-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Sun, 09 Sep 2018 07:42:14 -0400 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Sun, 9 Sep 2018 12:42:11 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w89Bg9PV16777324 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 9 Sep 2018 11:42:09 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D5C645204E; Sun, 9 Sep 2018 14:41:59 +0100 (BST) Received: from vajain21.in.ibm.com.com (unknown [9.199.52.245]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id E91EA5204F; Sun, 9 Sep 2018 14:41:57 +0100 (BST) From: Vaibhav Jain To: Frederic Barrat , Andrew Donnellan , Christophe Lombard Date: Sun, 9 Sep 2018 17:11:39 +0530 X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180909114140.9836-1-vaibhav@linux.ibm.com> References: <20180909114140.9836-1-vaibhav@linux.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 18090911-0028-0000-0000-000002F6ADAF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18090911-0029-0000-0000-000023B03ED2 Message-Id: <20180909114140.9836-3-vaibhav@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-09_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=864 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1807170000 definitions=main-1809090130 Subject: [Skiboot] [RFC 2/3] phb4/capp: Introduce 'stq-buffers' capp attribute override X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" CAPP uses PEC STQ buffers to communicate with the PSL/XSL on the CAPI card. Presently during CAPP init a static number of these STQ buffers are allocated to based on the link-width of the card which is x16 => 14 Buffers and x8 => 6 Buffers. However in certain circumstances it will be useful to be able to tune this value to improve card throughput. For example in case of Mellanox CX5 adapter (x8+ x8), we just assign 2 STQ Buffers to CAPP. Other cards may need different value for STQ Buffers to ensure optimal performance. Hence this patch introduces a capp attribute override named 'stq-buffers' that can be used to specify the number of CI Buffers to be reserved for CAPP traffic on the PHB. This value will then be used to configure CAPP 'Transport Control Register' as well as PEC's 'CAPP Control Register'. The valid values for this attribute are [1, 14]. Signed-off-by: Vaibhav Jain --- hw/phb4.c | 72 +++++++++++++++++++++++++++---------------------------- 1 file changed, 36 insertions(+), 36 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 80238ea6..4a9e9847 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -3839,7 +3839,7 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) { uint64_t reg; uint32_t offset; - uint8_t link_width_x16 = 1; + uint8_t link_width_x16 = 1, stq_eng = 0; offset = PHB4_CAPP_REG_OFFSET(p); @@ -3887,6 +3887,17 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) reg |= PPC_BIT(50); xscom_write(p->chip_id, SNOOP_CONTROL + offset, reg); + + /* Calculate the number of stq engines needed */ + if (capp_eng & CAPP_MAX_STQ_ENGINES) { + /* 14 CAPP msg engines or 6 based on link width */ + stq_eng = link_width_x16 ? 14 : 6; + } else if (capp_eng & CAPP_MIN_STQ_ENGINES) { + /* 2 CAPP msg engines */ + stq_eng = 2; + } + stq_eng = (capp_get_override(&p->phb, "stq-buffers", stq_eng) & 0xF); + /* Transport Control Register */ xscom_read(p->chip_id, TRANSPORT_CONTROL + offset, ®); if (p->index == CAPP0_PHB_INDEX) { @@ -3894,41 +3905,27 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng) reg |= PPC_BITMASK(10, 13); /* Send Packet Timer Value */ reg &= ~PPC_BITMASK(14, 17); /* Set Max LPC CI store buffer to zeros */ reg &= ~PPC_BITMASK(18, 21); /* Set Max tlbi divider */ - if (capp_eng & CAPP_MIN_STQ_ENGINES) { - /* 2 CAPP msg engines */ - reg |= PPC_BIT(58); - reg |= PPC_BIT(59); - reg |= PPC_BIT(60); - } - if (capp_eng & CAPP_MAX_STQ_ENGINES) { - /* 14 CAPP msg engines */ - reg |= PPC_BIT(60); - } - reg |= PPC_BIT(62); } if (p->index == CAPP1_PHB_INDEX) { reg |= PPC_BIT(4); /* Send Packet Timer Value */ - reg &= ~PPC_BIT(10); /* Set CI Store Buffer Threshold=5 */ - reg |= PPC_BIT(11); /* Set CI Store Buffer Threshold=5 */ - reg &= ~PPC_BIT(12); /* Set CI Store Buffer Threshold=5 */ - reg |= PPC_BIT(13); /* Set CI Store Buffer Threshold=5 */ + + reg &= ~PPC_BITMASK(10, 13);/* CI Store Buffer Threshold=5 */ + reg |= PPC_BIT(11) | PPC_BIT(13); + reg &= ~PPC_BITMASK(14, 17); /* Set Max LPC CI store buffer to zeros */ reg &= ~PPC_BITMASK(18, 21); /* Set Max tlbi divider */ - if (capp_eng & CAPP_MIN_STQ_ENGINES) { - /* 2 CAPP msg engines */ - reg |= PPC_BIT(59); - reg |= PPC_BIT(60); - - } else if (capp_eng & CAPP_MAX_STQ_ENGINES) { + } - if (link_width_x16) - /* 14 CAPP msg engines */ - reg |= PPC_BIT(60) | PPC_BIT(62); - else - /* 6 CAPP msg engines */ - reg |= PPC_BIT(60); - } + reg &= ~PPC_BITMASK(58, 62); + /* encode stq engines in the reg */ + if (stq_eng <= 6) { + reg |= ((7 - stq_eng + 1) & 0x7) << 2; + } else if (stq_eng <= 14) { + reg |= ((15 - stq_eng + 1) & 0xF) << 2; + /* Mark CI Store Buffers Avail */ + reg |= PPC_BIT(62); } + PHBINF(p, "CAPP: Using %d STQ Engines. stq=0x%016llX\n", stq_eng, reg); xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg); /* The transport control register needs to be loaded in two @@ -4103,7 +4100,7 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, * 14 and will be assigned in the order of STQ 15 to 2. * - 0-47 (Read machines) are available for capp use. */ - stq_eng = 0x000E000000000000ULL; /* 14 CAPP msg engines */ + stq_eng = 14; /* 14 CAPP msg engines */ dma_eng = 0x0000FFFFFFFFFFFFULL; /* 48 CAPP Read machines */ } @@ -4117,7 +4114,7 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, * 14 and will be assigned in the order of STQ 15 to 2. * - 0-47 (Read machines) are available for capp use. */ - stq_eng = 0x000E000000000000ULL; + stq_eng = 14; dma_eng = 0x0000FFFFFFFFFFFFULL; } else { @@ -4126,20 +4123,23 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number, * be 6 and will be assigned in the order of 7 to 2. * - 0-30 (Read machines) are available for capp use. */ - stq_eng = 0x0006000000000000ULL; + stq_eng = 6; + /* 30 Read machines for CAPP Minus 20-27 for DMA */ dma_eng = 0x0000FFFFF00E0000ULL; } } if (capp_eng & CAPP_MIN_STQ_ENGINES) - stq_eng = 0x0002000000000000ULL; /* 2 capp msg engines */ + stq_eng = 2; /* 2 capp msg engines */ - /* CAPP Control Register. Enable CAPP Mode */ - reg = 0x8000000000000000ULL; /* PEC works in CAPP Mode */ - reg |= stq_eng; if (capp_eng & CAPP_MAX_DMA_READ_ENGINES) dma_eng = 0x0000F00000000000ULL; /* 4 CAPP Read machines */ + + /* CAPP Control Register. Enable CAPP Mode */ + reg = 0x8000000000000000ULL; /* PEC works in CAPP Mode */ + reg |= (capp_get_override(&p->phb, "stq-buffers", stq_eng) & 0xF) + << (64 - 16); reg |= dma_eng; xscom_write(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, reg);