[RFC,2/3] phb4/capp: Introduce 'stq-buffers' capp attribute override

Message ID 20180909114140.9836-3-vaibhav@linux.ibm.com
State New
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Series
  • phb4/capp: Provide user tunable for STQ/DMA engine allocation
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Commit Message

Vaibhav Jain Sept. 9, 2018, 11:41 a.m.
CAPP uses PEC STQ buffers to communicate with the PSL/XSL on the CAPI
card. Presently during CAPP init a static number of these STQ buffers
are allocated to based on the link-width of the card which is x16 =>
14 Buffers and x8 => 6 Buffers.

However in certain circumstances it will be useful to be able to tune
this value to improve card throughput. For example in case of Mellanox
CX5 adapter (x8+ x8), we just assign 2 STQ Buffers to CAPP. Other
cards may need different value for STQ Buffers to ensure optimal
performance.

Hence this patch introduces a capp attribute override named
'stq-buffers' that can be used to specify the number of CI Buffers
to be reserved for CAPP traffic on the PHB. This value will then be
used to configure CAPP 'Transport Control Register' as well as PEC's
'CAPP Control Register'. The valid values for this attribute are [1,
14].

Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
---
 hw/phb4.c | 72 +++++++++++++++++++++++++++----------------------------
 1 file changed, 36 insertions(+), 36 deletions(-)

Comments

Frederic Barrat Sept. 11, 2018, 3:39 p.m. | #1
Le 09/09/2018 à 13:41, Vaibhav Jain a écrit :
> +
> +	/* Calculate the number of stq engines needed */
> +	if (capp_eng & CAPP_MAX_STQ_ENGINES) {
> +		/* 14 CAPP msg engines or 6 based on link width */
> +		stq_eng = link_width_x16 ? 14 : 6;
> +	} else if (capp_eng & CAPP_MIN_STQ_ENGINES) {
> +		/* 2 CAPP msg engines */
> +		stq_eng = 2;
> +	}
> +	stq_eng = (capp_get_override(&p->phb, "stq-buffers", stq_eng) & 0xF);
> +

This is what I like the most. Have a policy for the number of engines, 
then build set the CAPP setup for it. But we still have 2 flows: one for 
PEC, one for CAPP. Can't we just have that code at the beginning of 
enable_capi_mode() and pass the engine count to the capp setup function? 
Only one read ofthe nvram setting should be needed. Same thing to figure 
out the link width for PEC2.

And same logic applies for the dma engine count (next patch).
Then hopefully, next time we update the engine counts, the PEC and CAPP 
setups will be computed correctly the first time :-)

   Fred

Patch

diff --git a/hw/phb4.c b/hw/phb4.c
index 80238ea6..4a9e9847 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -3839,7 +3839,7 @@  static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 {
 	uint64_t reg;
 	uint32_t offset;
-	uint8_t link_width_x16 = 1;
+	uint8_t link_width_x16 = 1, stq_eng = 0;
 
 	offset = PHB4_CAPP_REG_OFFSET(p);
 
@@ -3887,6 +3887,17 @@  static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 	reg |= PPC_BIT(50);
 	xscom_write(p->chip_id, SNOOP_CONTROL + offset, reg);
 
+
+	/* Calculate the number of stq engines needed */
+	if (capp_eng & CAPP_MAX_STQ_ENGINES) {
+		/* 14 CAPP msg engines or 6 based on link width */
+		stq_eng = link_width_x16 ? 14 : 6;
+	} else if (capp_eng & CAPP_MIN_STQ_ENGINES) {
+		/* 2 CAPP msg engines */
+		stq_eng = 2;
+	}
+	stq_eng = (capp_get_override(&p->phb, "stq-buffers", stq_eng) & 0xF);
+
 	/* Transport Control Register */
 	xscom_read(p->chip_id, TRANSPORT_CONTROL + offset, &reg);
 	if (p->index == CAPP0_PHB_INDEX) {
@@ -3894,41 +3905,27 @@  static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 		reg |= PPC_BITMASK(10, 13); /* Send Packet Timer Value */
 		reg &= ~PPC_BITMASK(14, 17); /* Set Max LPC CI store buffer to zeros */
 		reg &= ~PPC_BITMASK(18, 21); /* Set Max tlbi divider */
-		if (capp_eng & CAPP_MIN_STQ_ENGINES) {
-			/* 2 CAPP msg engines */
-			reg |= PPC_BIT(58);
-			reg |= PPC_BIT(59);
-			reg |= PPC_BIT(60);
-		}
-		if (capp_eng & CAPP_MAX_STQ_ENGINES) {
-			/* 14 CAPP msg engines */
-			reg |= PPC_BIT(60);
-		}
-		reg |= PPC_BIT(62);
 	}
 	if (p->index == CAPP1_PHB_INDEX) {
 		reg |= PPC_BIT(4); /* Send Packet Timer Value */
-		reg &= ~PPC_BIT(10); /* Set CI Store Buffer Threshold=5 */
-		reg |= PPC_BIT(11);  /* Set CI Store Buffer Threshold=5 */
-		reg &= ~PPC_BIT(12); /* Set CI Store Buffer Threshold=5 */
-		reg |= PPC_BIT(13);  /* Set CI Store Buffer Threshold=5 */
+
+		reg &= ~PPC_BITMASK(10, 13);/* CI Store Buffer Threshold=5 */
+		reg |= PPC_BIT(11) | PPC_BIT(13);
+
 		reg &= ~PPC_BITMASK(14, 17); /* Set Max LPC CI store buffer to zeros */
 		reg &= ~PPC_BITMASK(18, 21); /* Set Max tlbi divider */
-		if (capp_eng & CAPP_MIN_STQ_ENGINES) {
-			/* 2 CAPP msg engines */
-			reg |= PPC_BIT(59);
-			reg |= PPC_BIT(60);
-
-		} else if (capp_eng & CAPP_MAX_STQ_ENGINES) {
+	}
 
-			if (link_width_x16)
-				/* 14 CAPP msg engines */
-				reg |= PPC_BIT(60) | PPC_BIT(62);
-			else
-				/* 6 CAPP msg engines */
-				reg |= PPC_BIT(60);
-		}
+	reg &= ~PPC_BITMASK(58, 62);
+	/* encode stq engines in the reg */
+	if (stq_eng <= 6) {
+		reg |= ((7 - stq_eng + 1) & 0x7) << 2;
+	} else if (stq_eng <= 14) {
+		reg |= ((15 - stq_eng + 1) & 0xF) << 2;
+		/* Mark CI Store Buffers Avail */
+		reg |= PPC_BIT(62);
 	}
+	PHBINF(p, "CAPP: Using %d STQ Engines. stq=0x%016llX\n", stq_eng, reg);
 	xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);
 
 	/* The transport control register needs to be loaded in two
@@ -4103,7 +4100,7 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 		 * 14 and will be assigned in the order of STQ 15 to 2.
 		 * - 0-47 (Read machines) are available for capp use.
 		 */
-		stq_eng = 0x000E000000000000ULL; /* 14 CAPP msg engines */
+		stq_eng = 14; /* 14 CAPP msg engines */
 		dma_eng = 0x0000FFFFFFFFFFFFULL; /* 48 CAPP Read machines */
 	}
 
@@ -4117,7 +4114,7 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 			 * 14 and will be assigned in the order of STQ 15 to 2.
 			 * - 0-47 (Read machines) are available for capp use.
 			 */
-			stq_eng = 0x000E000000000000ULL;
+			stq_eng = 14;
 			dma_eng = 0x0000FFFFFFFFFFFFULL;
 		} else {
 
@@ -4126,20 +4123,23 @@  static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 			 * be 6 and will be assigned in the order of 7 to 2.
 			 * - 0-30 (Read machines) are available for capp use.
 			 */
-			stq_eng = 0x0006000000000000ULL;
+			stq_eng = 6;
+
 			/* 30 Read machines for CAPP Minus 20-27 for DMA */
 			dma_eng = 0x0000FFFFF00E0000ULL;
 		}
 	}
 
 	if (capp_eng & CAPP_MIN_STQ_ENGINES)
-		stq_eng = 0x0002000000000000ULL; /* 2 capp msg engines */
+		stq_eng = 2; /* 2 capp msg engines */
 
-	/* CAPP Control Register. Enable CAPP Mode */
-	reg = 0x8000000000000000ULL; /* PEC works in CAPP Mode */
-	reg |= stq_eng;
 	if (capp_eng & CAPP_MAX_DMA_READ_ENGINES)
 		dma_eng = 0x0000F00000000000ULL; /* 4 CAPP Read machines */
+
+	/* CAPP Control Register. Enable CAPP Mode */
+	reg = 0x8000000000000000ULL; /* PEC works in CAPP Mode */
+	reg |= (capp_get_override(&p->phb, "stq-buffers", stq_eng) & 0xF)
+		<< (64 - 16);
 	reg |= dma_eng;
 	xscom_write(p->chip_id, p->pe_xscom + XPEC_NEST_CAPP_CNTL, reg);