Patchwork [i386] : Fix PR 49104 - bootstrap failure on AMD K6-2 with illegal instruction (cmove) in stage2

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Submitter Uros Bizjak
Date May 22, 2011, 7:08 p.m.
Message ID <BANLkTikRWBETb6JJKuTcnBy3haTJWBQw_w@mail.gmail.com>
Download mbox | patch
Permalink /patch/96764/
State New
Headers show

Comments

Uros Bizjak - May 22, 2011, 7:08 p.m.
Hello!

The problem is in optimized search_line_mmx function in libcpp/lex.c.
This function is compiled for SSE target, so cmove instructions are
automatically enabled.  In addition, "pmovmskb" instruction is part of
"AMD extensions to MMX" instruction set, marked by bit 22 in register
%edx from cpuid 0x8000 0001 function.

Attached patch fixes all these issues.  Please note, that bit_CMOV is
also returned in %edx from cpuid 0x8000 0001 function, so we don't
have to check for features, scattered in multiple places...

gcc/ChangeLog:

2011-05-22  Uros Bizjak  <ubizjak@gmail.com>

	PR target/49104
	* config/i386/cpuid.h (bit_MMXEXT): New define.

libcpp/ChangeLog:

2011-05-22  Uros Bizjak  <ubizjak@gmail.com>

	PR target/49104
	* lex.c (init_vectorized_lexer): Do not set "minimum" when __3dNOW_A__
	is defined.  Check bit_MMXEXT and bit_CMOV to use search_line_mmx.

Patch was compile tested on x86_64-pc-linux-gnu, will be committed to
4.6 and SVN mainline.

Uros.

Patch

Index: gcc/config/i386/cpuid.h
===================================================================
--- gcc/config/i386/cpuid.h	(revision 174030)
+++ gcc/config/i386/cpuid.h	(working copy)
@@ -57,6 +57,7 @@ 
 #define bit_TBM         (1 << 21)
 
 /* %edx */
+#define bit_MMXEXT	(1 << 22)
 #define bit_LM		(1 << 29)
 #define bit_3DNOWP	(1 << 30)
 #define bit_3DNOW	(1 << 31)
Index: libcpp/lex.c
===================================================================
--- libcpp/lex.c	(revision 174030)
+++ libcpp/lex.c	(working copy)
@@ -294,7 +294,7 @@  static const char repl_chars[4][16] __at
 /* A version of the fast scanner using MMX vectorized byte compare insns.
 
    This uses the PMOVMSKB instruction which was introduced with "MMX2",
-   which was packaged into SSE1; it is also present in the AMD 3dNOW-A
+   which was packaged into SSE1; it is also present in the AMD MMX
    extension.  Mark the function as using "sse" so that we emit a real
    "emms" instruction, rather than the 3dNOW "femms" instruction.  */
 
@@ -488,7 +488,7 @@  init_vectorized_lexer (void)
   minimum = 3;
 #elif defined(__SSE2__)
   minimum = 2;
-#elif defined(__SSE__) || defined(__3dNOW_A__)
+#elif defined(__SSE__)
   minimum = 1;
 #endif
 
@@ -505,7 +505,8 @@ 
     }
   else if (__get_cpuid (0x80000001, &dummy, &dummy, &dummy, &edx))
     {
-      if (minimum == 1 || edx & bit_3DNOWP)
+      if (minimum == 1
+	  || (edx & (bit_MMXEXT | bit_CMOV)) == (bit_MMXEXT | bit_CMOV))
 	impl = search_line_mmx;
     }