phb4/capp: Use link width to allocate STQ engines to CAPP

Message ID 20180908064654.8995-1-vaibhav@linux.ibm.com
State Accepted
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  • phb4/capp: Use link width to allocate STQ engines to CAPP
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Commit Message

Vaibhav Jain Sept. 8, 2018, 6:46 a.m.
Update phb4_init_capp_regs() to allocates STQ Engines to CAPP/PEC2
based on link width instead of always assuming it to x8.

Also re-factor the function slightly to evaluate the link-width only
once and cache it so that it can also be used to allocate DMA read
engines.

Cc: stable
Fixes: 47c09cdfe7a3("phb4/capp: Calculate STQ/DMA read engines based on link-width for PEC")
Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
---
 hw/phb4.c | 46 +++++++++++++++++++++++++++++-----------------
 1 file changed, 29 insertions(+), 17 deletions(-)

Comments

Frederic Barrat Sept. 11, 2018, 3:41 p.m. | #1
Le 08/09/2018 à 08:46, Vaibhav Jain a écrit :
> Update phb4_init_capp_regs() to allocates STQ Engines to CAPP/PEC2
> based on link width instead of always assuming it to x8.
> 
> Also re-factor the function slightly to evaluate the link-width only
> once and cache it so that it can also be used to allocate DMA read
> engines.
> 
> Cc: stable
> Fixes: 47c09cdfe7a3("phb4/capp: Calculate STQ/DMA read engines based on link-width for PEC")
> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
> ---

I believe this is correct. The code starts looking like spaghetti, but 
you're addressing that in your RFC.
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>


>   hw/phb4.c | 46 +++++++++++++++++++++++++++++-----------------
>   1 file changed, 29 insertions(+), 17 deletions(-)
> 
> diff --git a/hw/phb4.c b/hw/phb4.c
> index d1245dce..80238ea6 100644
> --- a/hw/phb4.c
> +++ b/hw/phb4.c
> @@ -3839,9 +3839,20 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
>   {
>   	uint64_t reg;
>   	uint32_t offset;
> +	uint8_t link_width_x16 = 1;
>   
>   	offset = PHB4_CAPP_REG_OFFSET(p);
>   
> +	/* Calculate the phb link width if card is attached to PEC2 */
> +	if (p->index == CAPP1_PHB_INDEX) {
> +		/* Check if PEC2 is in x8 or x16 mode.
> +		 * PEC0 is always in x16
> +		 */
> +		xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, &reg);
> +		link_width_x16 = ((reg & XPEC_PCI2_IOVALID_MASK) ==
> +				  XPEC_PCI2_IOVALID_X16);
> +	}
> +
>   	/* APC Master PowerBus Control Register */
>   	xscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, &reg);
>   	reg |= PPC_BIT(0); /* enable cResp exam */
> @@ -3907,10 +3918,15 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
>   			/* 2 CAPP msg engines */
>   			reg |= PPC_BIT(59);
>   			reg |= PPC_BIT(60);
> -		}
> -		if (capp_eng & CAPP_MAX_STQ_ENGINES) {
> -			/* 6 CAPP msg engines */
> -			reg |= PPC_BIT(60);
> +
> +		} else if (capp_eng & CAPP_MAX_STQ_ENGINES) {
> +
> +			if (link_width_x16)
> +				/* 14 CAPP msg engines */
> +				reg |= PPC_BIT(60) | PPC_BIT(62);
> +			else
> +				/* 6 CAPP msg engines */
> +				reg |= PPC_BIT(60);
>   		}
>   	}
>   	xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);
> @@ -3951,20 +3967,16 @@ static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
>   
>   		if (capp_eng & CAPP_MAX_DMA_READ_ENGINES) {
>   			reg = 0xF000000000000000ULL;
> +		} else if (link_width_x16) {
> +			/* 0-47 (Read machines) are available for
> +			 * capp use
> +			 */
> +			reg = 0x0000FFFFFFFFFFFFULL;
>   		} else {
> -			/* Check if PEC is in x8 or x16 mode */
> -			xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, &reg);
> -			if ((reg & XPEC_PCI2_IOVALID_MASK) ==
> -			    XPEC_PCI2_IOVALID_X16)
> -				/* 0-47 (Read machines) are available for
> -				 * capp use
> -				 */
> -				reg = 0x0000FFFFFFFFFFFFULL;
> -			else
> -				/* Set 30 Read machines for CAPP Minus
> -				 * 20-27 for DMA
> -				 */
> -				reg = 0xFFFFF00E00000000ULL;
> +			/* Set 30 Read machines for CAPP Minus
> +			 * 20-27 for DMA
> +			 */
> +			reg = 0xFFFFF00E00000000ULL;
>   		}
>   		xscom_write(p->chip_id, APC_FSM_READ_MASK + offset, reg);
>   		xscom_write(p->chip_id, XPT_FSM_RMM + offset, reg);
>
Stewart Smith Oct. 16, 2018, 7:55 a.m. | #2
Vaibhav Jain <vaibhav@linux.ibm.com> writes:
> Update phb4_init_capp_regs() to allocates STQ Engines to CAPP/PEC2
> based on link width instead of always assuming it to x8.
>
> Also re-factor the function slightly to evaluate the link-width only
> once and cache it so that it can also be used to allocate DMA read
> engines.
>
> Cc: stable
> Fixes: 47c09cdfe7a3("phb4/capp: Calculate STQ/DMA read engines based on link-width for PEC")
> Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
> ---
>  hw/phb4.c | 46 +++++++++++++++++++++++++++++-----------------
>  1 file changed, 29 insertions(+), 17 deletions(-)

Thanks!

Merged to master as of 2d7419274dfad55f1909fd9ad948764d23aef978
and to 6.0.x as of 84ca6d0ce15f539421c3b2d54d0466241505fe0f

Patch

diff --git a/hw/phb4.c b/hw/phb4.c
index d1245dce..80238ea6 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -3839,9 +3839,20 @@  static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 {
 	uint64_t reg;
 	uint32_t offset;
+	uint8_t link_width_x16 = 1;
 
 	offset = PHB4_CAPP_REG_OFFSET(p);
 
+	/* Calculate the phb link width if card is attached to PEC2 */
+	if (p->index == CAPP1_PHB_INDEX) {
+		/* Check if PEC2 is in x8 or x16 mode.
+		 * PEC0 is always in x16
+		 */
+		xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, &reg);
+		link_width_x16 = ((reg & XPEC_PCI2_IOVALID_MASK) ==
+				  XPEC_PCI2_IOVALID_X16);
+	}
+
 	/* APC Master PowerBus Control Register */
 	xscom_read(p->chip_id, APC_MASTER_PB_CTRL + offset, &reg);
 	reg |= PPC_BIT(0); /* enable cResp exam */
@@ -3907,10 +3918,15 @@  static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 			/* 2 CAPP msg engines */
 			reg |= PPC_BIT(59);
 			reg |= PPC_BIT(60);
-		}
-		if (capp_eng & CAPP_MAX_STQ_ENGINES) {
-			/* 6 CAPP msg engines */
-			reg |= PPC_BIT(60);
+
+		} else if (capp_eng & CAPP_MAX_STQ_ENGINES) {
+
+			if (link_width_x16)
+				/* 14 CAPP msg engines */
+				reg |= PPC_BIT(60) | PPC_BIT(62);
+			else
+				/* 6 CAPP msg engines */
+				reg |= PPC_BIT(60);
 		}
 	}
 	xscom_write(p->chip_id, TRANSPORT_CONTROL + offset, reg);
@@ -3951,20 +3967,16 @@  static void phb4_init_capp_regs(struct phb4 *p, uint32_t capp_eng)
 
 		if (capp_eng & CAPP_MAX_DMA_READ_ENGINES) {
 			reg = 0xF000000000000000ULL;
+		} else if (link_width_x16) {
+			/* 0-47 (Read machines) are available for
+			 * capp use
+			 */
+			reg = 0x0000FFFFFFFFFFFFULL;
 		} else {
-			/* Check if PEC is in x8 or x16 mode */
-			xscom_read(p->chip_id, XPEC_PCI2_CPLT_CONF1, &reg);
-			if ((reg & XPEC_PCI2_IOVALID_MASK) ==
-			    XPEC_PCI2_IOVALID_X16)
-				/* 0-47 (Read machines) are available for
-				 * capp use
-				 */
-				reg = 0x0000FFFFFFFFFFFFULL;
-			else
-				/* Set 30 Read machines for CAPP Minus
-				 * 20-27 for DMA
-				 */
-				reg = 0xFFFFF00E00000000ULL;
+			/* Set 30 Read machines for CAPP Minus
+			 * 20-27 for DMA
+			 */
+			reg = 0xFFFFF00E00000000ULL;
 		}
 		xscom_write(p->chip_id, APC_FSM_READ_MASK + offset, reg);
 		xscom_write(p->chip_id, XPT_FSM_RMM + offset, reg);