diff mbox series

[U-Boot,v1,4/4] MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE

Message ID 20180907170206.22586-5-daniel.schwierzeck@gmail.com
State Accepted
Delegated to: Daniel Schwierzeck
Headers show
Series MIPS: optimise cache initialization | expand

Commit Message

Daniel Schwierzeck Sept. 7, 2018, 5:02 p.m. UTC 
Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT
(or CONF_CM_CACHABLE_COW when a CM is available). There is no
need to make this configurable.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

---

 README                           | 14 --------------
 arch/mips/lib/cache_init.S       |  6 +-----
 include/configs/imgtec_xilfpga.h |  3 ---
 include/configs/pic32mzdask.h    |  3 ---
 scripts/config_whitelist.txt     |  1 -
 5 files changed, 1 insertion(+), 26 deletions(-)
diff mbox series

Patch

diff --git a/README b/README
index a91af2a189..c280b7a95f 100644
--- a/README
+++ b/README
@@ -528,20 +528,6 @@  The following options need to be configured:
 		pointer. This is needed for the temporary stack before
 		relocation.
 
-		CONFIG_SYS_MIPS_CACHE_MODE
-
-		Cache operation mode for the MIPS CPU.
-		See also arch/mips/include/asm/mipsregs.h.
-		Possible values are:
-			CONF_CM_CACHABLE_NO_WA
-			CONF_CM_CACHABLE_WA
-			CONF_CM_UNCACHED
-			CONF_CM_CACHABLE_NONCOHERENT
-			CONF_CM_CACHABLE_CE
-			CONF_CM_CACHABLE_COW
-			CONF_CM_CACHABLE_CUW
-			CONF_CM_CACHABLE_ACCELERATED
-
 		CONFIG_SYS_XWAY_EBU_BOOTCFG
 
 		Special option for Lantiq XWAY SoCs for booting from NOR flash.
diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 5616ee6dfd..cfad1d9c8a 100644
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -14,10 +14,6 @@ 
 #include <asm/cacheops.h>
 #include <asm/cm.h>
 
-#ifndef CONFIG_SYS_MIPS_CACHE_MODE
-#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
-#endif
-
 	.macro	f_fill64 dst, offset, val
 	LONG_S	\val, (\offset +  0 * LONGSIZE)(\dst)
 	LONG_S	\val, (\offset +  1 * LONGSIZE)(\dst)
@@ -331,7 +327,7 @@  l1_init:
 	and		t0, t0, t1
 	PTR_LI		t1, CKSEG1
 	or		t0, t0, t1
-	li		a0, CONFIG_SYS_MIPS_CACHE_MODE
+	li		a0, CONF_CM_CACHABLE_NONCOHERENT
 	jalr.hb		t0
 
 	/*
diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h
index 29b23fa40e..8e2d72323d 100644
--- a/include/configs/imgtec_xilfpga.h
+++ b/include/configs/imgtec_xilfpga.h
@@ -19,9 +19,6 @@ 
 /* CPU Timer rate */
 #define CONFIG_SYS_MIPS_TIMER_FREQ	50000000
 
-/* Cache Configuration */
-#define CONFIG_SYS_MIPS_CACHE_MODE	CONF_CM_CACHABLE_NONCOHERENT
-
 /*----------------------------------------------------------------------
  * Memory Layout
  */
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h
index d3775023d0..ec2e7743d9 100644
--- a/include/configs/pic32mzdask.h
+++ b/include/configs/pic32mzdask.h
@@ -16,9 +16,6 @@ 
 /* CPU Timer rate */
 #define CONFIG_SYS_MIPS_TIMER_FREQ	100000000
 
-/* Cache Configuration */
-#define CONFIG_SYS_MIPS_CACHE_MODE	CONF_CM_CACHABLE_NONCOHERENT
-
 /*----------------------------------------------------------------------
  * Memory Layout
  */
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 1a5606d123..b3cba57843 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -3435,7 +3435,6 @@  CONFIG_SYS_MEM_TOP_HIDE
 CONFIG_SYS_MFD
 CONFIG_SYS_MHZ
 CONFIG_SYS_MII_MODE
-CONFIG_SYS_MIPS_CACHE_MODE
 CONFIG_SYS_MIPS_TIMER_FREQ
 CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR